Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-27
2003-04-15
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S734000
Reexamination Certificate
active
06550030
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of testing of integrated circuit devices and, more particularly, to a method of testing the programmable logic blocks in a field programmable gate array.
BACKGROUND OF THE INVENTION
A field programmable gate array (FPGA) is a type of integrated circuit consisting of an array of programmable logic blocks interconnected by a programmable routing network and programmable input/output cells. Programming of the logic blocks, the routing network and the input/output cells is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application.
The present inventors have recently developed methods of built-in self-testing the array of programmable logic blocks and the programmable routing network in FPGAs at the device, board and system levels. These methods are set out in detail in pending U.S. patent application Ser. No. 08/729,117 now U.S. Pat. No. 5,991,907, Ser. No. 08/595,729 now abandoned and Ser. No. 09/109,123 now U.S. Pat. No. 6,202,182. The full disclosures in these patent applications are incorporated herein by reference.
In each of these prior methods, the reprogrammability of an FPGA is exploited so that the FPGA is configured exclusively with built-in self-test (BIST) logic during off-line testing and subsequently reconfigured to its normal operating configuration. In this way, testability at every level is achieved without overhead. In other words, the BIST logic simply “disappears” when the FPGA is reconfigured for its normal system function.
In addition to these off-line testing methods, the present inventors have also recently developed methods of testing and fault tolerant operation of the programmable logic blocks of FPGAs. These methods are set out in detail in pending U.S. patent application Ser. No. 09/261,776 now U.S. Pat. No. 6,256,758. The full disclosure in this patent application is also incorporated herein by reference.
Fault tolerant operation of FPGAs is most important in high-reliability and high-availability applications, such as, space missions or telecommunication network routers in which adaptive computing systems often rely on reconfigurable hardware to adapt system operation. In such applications, the FPGA hardware must work continuously and simply cannot be taken off-line for testing, maintenance, or repair.
When faults are detected and located in the FPGA hardware of these systems, the FPGA resources must be quickly reconfigured to continue operation in a diminished capacity or to avoid the identified faulty resources altogether. Necessarily, therefore, testing of the FPGA resources must be performed concurrently with normal system operation.
SUMMARY OF THE INVENTION
In accordance with the present invention, the method of testing field programmable gate arrays is carried out during normal on-line operation of the FPGA by configuring the FPGA resources into a working area and an initial self-testing area. The working area maintains normal operation of the FPGA throughout testing. Within the initial and subsequent self-testing areas, however, the programmable logic blocks are each tested, and their utilization adjusted, if required. Advantageously, the working area is substantially unaffected by testing, and testing time constraints are reduced since normal operation continues in the working area.
Within the self-testing areas, test patterns are generated and applied to each programmable logic block selected as a block under test. The output patterns of the selected programmable logic block under test are preferably compared to output patterns produced by an equivalently configured programmable logic block within the self-testing area receiving the same test patterns. This method is similar to the BIST techniques described in detail in the above noted pending patent applications incorporated herein by reference.
Based on the comparison of the output patterns of the logic blocks under test, fault status data is generated. Based on the fault status data, partially faulty programmable logic blocks are reconfigured to perform a non-faulty function of the logic block and further utilized. By reconfiguring partially faulty programmable logic blocks to avoid all functions or operational modes affected by the detected fault, the partially faulty logic blocks are allowed to continue to operate in a progressively diminished, although acceptable, capacity for specific operating modes. This type of testing and fault tolerant operation is described in detail in the above noted pending patent application incorporated herein by reference.
In accordance with an important aspect of the present invention, the initial self-testing area of the FPGA may be further divided into self-testing tiles. Specifically, the self-testing area may be divided into any number of equivalently configured self-testing tiles so long as each tile contains a sufficient amount of FPGA resources to complete testing. Advantageously, this allows concurrent testing of several tiles within the self-testing area, thus reducing the overall test time and fault latency.
Another important aspect of the present inventive method provides for the repeated reconfiguring of the programmable logic blocks within the self-testing area or self-testing tiles so that each logic block becomes a logic block under test at least once during testing. Preferably, the functions of the programmable logic blocks within the self-testing area, i.e., test pattern generator, output response analyzer, programmable logic block under test, and possibly spare programmable logic block, are systematically rotated during testing. In this manner, each programmable logic block is compared to at least two different programmable logic blocks during testing thus substantially eliminating the possibility of faulty blocks passing the tests.
Upon completion of testing of each of the programmable logic blocks located within the initial self-testing area, the FPGA is reconfigured so that a portion of the working area becomes a subsequent self-testing area, and the initial self-testing area becomes a portion of the working area. In other words, the self-testing area roves around the FPGA repeating the steps of testing and reconfiguring the programmable logic blocks in the self-testing areas until each portion of the working area, or the entire FPGA, is reconfigured as a subsequent self-testing area, tested, and its programmable logic blocks reconfigured. Advantageously, normal operation of the FPGA continues within the working area throughout testing and is uninterrupted by the testing conducted within the self-testing areas.
The steps of configuring, testing, and reconfiguring each programmable logic block under test, storing the subsequent fault status data, and roving the self-testing area around the FPGA under test for further testing are necessarily controlled by a test and reconfiguration controller and an associated storage medium. In operation, the test and reconfiguration controller accesses the FPGA during normal system operation and configures the FPGA with one of a plurality of test configurations stored in the associated storage medium.
As described above, a test pattern generator configured within the self-testing area or within each self-testing tile provides the necessary test patterns dependent upon the function or mode of operation of the programmable logic block under test. The output patterns of the programmable logic block under test are preferably compared to output patterns produced by an equivalently configured programmable logic block under test receiving identical test patterns.
The test and reconfiguration controller further repeatedly reconfigures the programmable logic blocks under test for testing in all possible modes of operation. The results of the test pattern comparisons for each mode of operation of the logic blocks under test along with the intended functional usage data for the blocks under test are stored in the storage m
Abramovici Miron
Stroud Charles E.
Chung Phung M.
Lattice Semiconductor Corp.
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