Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-02-14
2006-02-14
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000, C703S019000, C438S018000, C324S763010
Reexamination Certificate
active
07000163
ABSTRACT:
An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.
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Boluki Human
Dirks Juergen
Johanterwage Ludger F.
Lahner Juergen K.
Li Weidan
Christopher P. Maiorana P.C.
De'cady Albert
LSI Logic Corporation
Trimmings John P.
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