Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-06-16
2010-11-16
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
07836371
ABSTRACT:
An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 3783254 (1974-01-01), Eichelberger
patent: 3784907 (1974-01-01), Eichelberger
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4667339 (1987-05-01), Tubbs et al.
patent: 4817093 (1989-03-01), Jacobs et al.
patent: 5065090 (1991-11-01), Gheewala
patent: 5068881 (1991-11-01), Dervisoglu et al.
patent: 5155432 (1992-10-01), Mahoney
patent: 5202624 (1993-04-01), Gheewala et al.
patent: 5202625 (1993-04-01), Farwell
patent: 5206862 (1993-04-01), Chandra et al.
patent: 5254482 (1993-10-01), Fisch
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5369648 (1994-11-01), Nelson
patent: 5418470 (1995-05-01), Dagostino et al.
patent: 5423050 (1995-06-01), Taylor et al.
patent: 5428629 (1995-06-01), Gutman et al.
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5495486 (1996-02-01), Gheewala
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5617531 (1997-04-01), Crouch et al.
patent: 5630048 (1997-05-01), La Joie et al.
patent: 5642478 (1997-06-01), Chen et al.
patent: 5724505 (1998-03-01), Argade et al.
patent: 5737520 (1998-04-01), Gronlund et al.
patent: 5761489 (1998-06-01), Broseghini et al.
patent: 5771240 (1998-06-01), Tobin et al.
patent: 5805792 (1998-09-01), Swoboda et al.
patent: 5838163 (1998-11-01), Rostoker et al.
patent: 5850512 (1998-12-01), Song
patent: 5854996 (1998-12-01), Overhage et al.
patent: 5905738 (1999-05-01), Whetsel
patent: 5936876 (1999-08-01), Sugasawara
patent: 5941995 (1999-08-01), Morrison
patent: 5944841 (1999-08-01), Christie
patent: 5991898 (1999-11-01), Rajski et al.
patent: 6003107 (1999-12-01), Ranson et al.
patent: 6003142 (1999-12-01), Mori
patent: 6035262 (2000-03-01), Gibson et al.
patent: 6094729 (2000-07-01), Mann
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6125464 (2000-09-01), Jin
patent: 6131171 (2000-10-01), Whetsel
patent: 6167536 (2000-12-01), Mann
patent: 6182247 (2001-01-01), Herrmann et al.
patent: 6189140 (2001-02-01), Madduri
patent: 6247147 (2001-06-01), Beenstra et al.
patent: 6321320 (2001-11-01), Fleischman et al.
patent: 6374370 (2002-04-01), Bockhaus et al.
patent: 6460148 (2002-10-01), Veenstra et al.
patent: 6499123 (2002-12-01), McFarland et al.
patent: 6522985 (2003-02-01), Swoboda et al.
patent: 6564347 (2003-05-01), Mates
patent: 6687865 (2004-02-01), Dervisoglu et al.
patent: 6704889 (2004-03-01), Veenstra et al.
patent: 6782498 (2004-08-01), Tanizaki et al.
patent: 6964001 (2005-11-01), Dervisoglu et al.
patent: 2006/0064615 (2006-03-01), Dervisoglu et al.
“BIST TPG for Faults in System Backplanes”; Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997, pp. 406-413.
“Design of Self-Diagnostic Boards by Multiple Signature Analysis”; IEEE Transactions on Computers, vol. 42, No. 9, Sep. 1993, pp. 1035-1044.
“Using Scan Technology for Debug and Diagnostics in a Workstation Environment”; Proceedings of the International Test Conference, 1988, Sep. 1988, pp. 976-986.
Arat Vacit
Cooke Laurence H.
Dervisoglu Bulent
Connolly Bove & Lodge & Hutz LLP
Ton David
LandOfFree
On-chip service processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with On-chip service processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-chip service processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4187587