Method and apparatus to reduce the size of programmable...

Method and apparatus to test memory

Method and arrangement for controlling multiple test access...

Method and arrangement for controlling multiply-activated...

Method and arrangement for hierarchical control of multiple...

Method and arrangement for testing digital circuits

Method and BIST architecture for fast memory testing in...

Method and circuit arrangement for testing electrical modules

Method and circuit arrangement for testing electrical modules

Method and circuit for at-speed testing of scan circuits

Method and circuit for parametric testing of integrated...

Method and circuit for scan testing latch based random...

Method and circuit for testing a chip

Method and circuit using boundary scan cells for design...

Method and configuration for protecting data during a...

Method and device for collecting output logic values from a...

Method and device for selecting the operating mode of an...

Method and device for selecting the operating mode of an...

Method and device for setting a plurality of test modes using ex

Method and device for simultaneous testing of a plurality of...