Method and circuit for at-speed testing of scan circuits

Details Method and circuit for at-speed testing of scan circuits Method and circuit for at-speed testing of scan circuits

2007-03-20

2007-03-20

Kerveros, James C. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10739055

ABSTRACT:
An improvement in a scan testing method for testing a circuit having memory elements arranged into one or more scan chains, the scan testing method having a shift phase for serially loading test patterns into the scan chains and serially unloading test response patterns from the scan chains and a capture phase for capturing the response of the circuit to the test pattern, includes, during the capture phase, connecting the serial output of each scan chain to its serial input and applying a predetermined number of capture clock cycles with the memory elements configured in a non-capture mode for all but the last capture clock cycle and configured in capture mode for the last capture clock cycle.

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patent: 2003/0084390 (2003-05-01), Tamarapalli et al.

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