Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-04-26
2003-09-23
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C708S254000
Reexamination Certificate
active
06625767
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronic circuit testing, and, more particularly, to a method and device for collecting output logic values from a logic circuit in an electronic circuit.
BACKGROUND OF THE INVENTION
The term “logic unit” as used throughout the description encompasses a set of logic gates connected together to provide a given logic function in an electronic circuit. This is more specifically the case with a combinatory logic function. The invention can also apply to a logic unit which executes a sequential logic function. Moreover, the term “electronic circuit” is to be understood in its broadest sense. Electronic circuit encompasses all discrete (packaged) electronic components and any construction from such components mounted on a printed circuit to form a functional unit, any unitary component implanted on a semiconductor substrate (i.e., an on-chip device), and any construction from such components.
FIG. 1
is a circuit diagram of a prior art device for collecting output values from a logic unit. In the figure, a logic unit to be tested is symbolized by a substantially oval shape
10
. It is included in an electronic circuit
5
. The logic circuits of the electronic circuit
5
, which operate upstream of the logic unit
10
, are symbolized by a substantially oval shape
20
. The logic unit
10
includes n inputs designated E
1
, . . . , En and p outputs designated S
1
, . . . , Sp.
The means for testing the logic unit
10
include a device for collecting output values of that unit, which includes p test cells designated CT′
1
, . . . , CT′p in accordance with the IEEE 1149.1b-1994 standard (known as the JTAG standard). These test cells are connected in the following manner. First, they are connected in parallel to the respective p outputs S
1
, . . . , Sp of the logic unit
10
such that in the electronic circuit's normal operating mode (normal mode), the output values of the logic unit
10
are loaded into the test cells. Second, the test cells are connected in series with one another to form a shift register for propagating output values to a node TDO for collecting these values in a specific operating mode of the device known as the test mode. The test cells then form an ordered chain along the propagation direction of the logic values in the shift register they form, i.e., from left to right as shown in the figure. By convention, the terms rank, first, last, following and preceding are used with reference to this ordered chain.
In the test mode, the thus-formed shift register serves to collect the output values of the logic unit
10
so that they can be analyzed by a test instrument. To this end, the electronic circuit includes a special output pin connected to node TDO for implementing the test mode in accordance with the boundary scan test mode. Other identical test cells (not shown) are similarly connected to inputs E
1
, . . . , En of the logic unit
10
. They also form a shift register which, in a test mode, serves to input test vectors on these inputs from a special serial input TDI of the circuit (not shown).
Different types of test cells are known in the prior art. One which is particularly widespread and shown in
FIG. 1
(CT′
1
to CT′p) includes a D-type flip-flop responsive to a signal edge (transition from one logic state to the other), as indicated by the > symbol shown at the clock input CP of the cell. In practice, the electronic circuit already includes such flip-flops for sampling the outputs in the normal mode.
The JTAG standard causes these existing flip-flops to fulfill another function in the test mode, namely that of an element of a shift register for propagating the logic values from the outputs to the collecting node. In other words, a test cell is adapted from a flip-flop already present in the electronic circuit. In addition to the D and CP inputs and the Q output of the D-type flip-flop, a test cell includes an input TI and an input TE.
The Q output of a D-type flip-flop of a given cell is connected to an input TI (known as the serial input in the JTAG standard) of the following cell, and to the input of one of the logic circuits of the electronic circuits
5
which are operative upstream of the logic unit
10
. In
FIG. 1
, the logic circuitry is shown symbolically by an oval
30
. Each cell is connected by an input D (known as the parallel input in the JTAG standard) to one of the outputs S
1
, . . . , Sp of unit
10
.
The clock input CP of each cell receives a clock signal CLOCK. In addition, an input TE (known as the test input in the JTAG standard) of each cell receives a same and unique test activation signal TEST_MODE. This signal enables the control of a multiplexer which selects the inputs D or TI whose logic value is loaded into the flip-flop when an edge of the CLOCK signal appears at input CP. In other words, the CLOCK signal serves to activate the flip-flop in two different ways depending on the TEST_MODE signal.
In the normal mode, the clock signal serves to load the instantaneous value of the outputs S
1
, . . . , Sp of logic unit
10
respectively in the flip-flops of the test cells CT′
1
, . . . , CT′p. In the test mode, it also serves to activate the shift register formed by test cells CT′
1
to CT′p. In both cases, flip-flops CT′
1
to CT′p are activated by the edges of the CLOCK signal applied to their inputs CP.
A particular problem arises with electronic circuits which, for reasons connected with their technology, do not include flip-flops responsive to a signal edge, but only latches responsive to a signal level. A signal level is understood to mean the value of a potential referenced with respect to ground which is associated to a given logic state. Indeed, a device such as described above could not operate with a latch responsive to a signal level instead of a flip-flop responsive to a signal edge. Only the logic value loaded into the first test cell CT′
1
would be collected directly at node TDO on condition that the TEST_MODE and CLOCK signals were simultaneously high, whereas the logic values loaded into the other test cells would be lost.
For this reason, test cells of another type are used for this circuit. These test cells each include two latches responsive to a signal level and arranged such that one of them operates as a master latch and the other as a slave latch. However, such cells take up a lot of space on the semiconductor substrate on which the electronic circuit is formed.
SUMMARY OF THE INVENTION
An object of the invention is to provide an approach for collecting output logic values from a logic unit within an electronic circuit which overcomes the above-mentioned drawbacks.
This object is achieved in accordance with the invention using a method for collecting logic values from outputs of a logic unit having n inputs and p outputs included within an electronic circuit. The step of collecting is performed by means of p test cells connected in parallel to the respective p outputs of the logic unit such that the logic values of the outputs of the logic unit are loaded in the test cells in a normal mode, and the p test cells are connected in series with each other so as to form a shift register for propagating logic values of outputs of the logic unit to a collecting node in a test mode.
The method further includes a first phase wherein the logic values of one out of two outputs are propagated in the shift register. In a second phase, the logic values of the other outputs of the logic unit are propagated in the shift register. The logic values of the outputs of the logic unit are reloaded in the test cells between the first and second phase.
The invention also provides a device for implementing the above-defined method. The invention further provides an electronic circuit comprising at least one logic unit and such a device for collecting output logic values from the logic unit. Advantageously, it is possible to design an electronic circuit in which each test cell comprises one
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
De'cady Albert
Jorgenson Lisa K.
STMicroelectronics SA
Whittington Anthony T.
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