Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-04-01
2002-05-07
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S726000, C714S727000
Reexamination Certificate
active
06385749
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to testing integrated circuits (ICs) and, more particularly, to IC test methods and arrangements involving multiple test access port controllers, such as used in connection with IEEE JTAG standards.
BACKGROUND OF THE INVENTION
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A wide variety of techniques have been used in IC devices to ensure that, once they are manufactured, they operate fully in compliance with their intended design and implementation specifications. Many of the more complex IC designs include circuits that permit in-circuit testing via the IC access pins. The IEEE 1149.1 JTAG recommendation, for example, provides a test circuit architecture for use inside such ICs. This architecture includes a test access port (TAP) controller coupled to the IC pins for providing access to and for controlling various standard features designed into such ICs. Some of these features are internal scan, boundary scan, built-in test and emulation.
The JTAG recommendation was developed with the understanding that such IC designs would be using only one test access port controller. Sometime after its initial development, however, many IC's are being designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller. Typically, separate IC pins are used to select one of the TAP controllers for testing and/or debugging the IC. This is problematic, however, in IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins.
One approach that attempts to overcome such difficulty involves use of an internally implemented circuit for selecting which of the TAP controllers is activated during a test/debug mode of operation inside the TAP controller itself. This approach requires a change to the existing structure of the TAP controllers so that special signals can be drawn from and fed to each TAP controller, and requires that each TAP controller have knowledge that it is enabled at a given time. For many applications, however, changing the design of the established TAP controller is expensive. Further, for certain applications, requiring that each TAP controller have knowledge that it is enabled at a given time adversely removes a desired degree of transparency.
For further information concerning with the above issues, reference may be made to an article entitled, “An IEEE 1149.1 Based Test Access Architecture for ICs with Embedded Cores,” by Lee Whetsel, and to IEEE Std. 1149.1-1990, and 1149.1-1993, each of which is incorporated herein by reference.
SUMMARY
According to various aspects of the present invention, embodiments thereof are exemplified in the form of methods and arrangements for controlling an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller. Such embodiments are useful in connection with IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins, and can be implemented to avoid changing existing structures of TAP controllers.
One specific implementation is directed to a circuit control arrangement for a multi-core IC having a limited number of access pins for selecting functions internal to the IC. The circuit control arrangement includes multiple test-access port (TAP) controllers and an output circuit. Each TAP controller couples to a common interface, receives input signals indicating if the TAP controller is enabled, and generates status and test signals. The output control circuit includes a TAP link module and is responsive to each of the multiple TAP controllers and configured and arranged to output one of the test signals respectively provided by the multiple TAP controllers. The TAP link module includes an output coupled to the input of each multiple TAP controller, provides the input signals and maintains one of the TAP controllers enabled at a given time.
A more specific implementation of the above circuit control arrangement, the TAP link module is adapted to respond to the status signal provided by each of the multiple TAP controllers by transitioning enablement between the TAP controllers and to signal to the output control circuit which one of the test signals respectively provided by the multiple TAP controllers to output.
In other more specific implementations, the common interface is compatible with an IEEE JTAG recommendation, and/or carries some or all of the JTAG-recommended interface signals and signal definitions.
Another aspect of the present invention is directed to a method for controlling multiple test-access port (TAP) controllers coupled to a common interface for a multi-core IC having a limited number of access pins for selecting functions internal to the IC. The method comprises: at each of the multiple TAP controllers, receiving input signals, determining if the TAP controller is enabled, and generating status and test signals; in response to each of the multiple TAP controllers, outputting one of the test signals respectively provided by the multiple TAP controllers; and at the input of each of the multiple TAP controllers, providing the input signals and for maintaining one of the TAP controllers enabled at a given time.
Yet another aspect of the present invention is directed to use in a multi-core IC having a limited number of access pins for selecting functions internal to the IC, with a circuit control arrangement in the IC comprising: multiple test-access port (TAP) controllers, each TAP controller configured and arranged to couple to a common interface, to receive input signals indicating if the TAP controller is enabled, and to generate status and test signals; a TAP link module coupled to the input of each multiple TAP controller, and configured and arranged to provide the input signals and to maintain one of the TAP controllers enabled at a given time, the TAP link module including: an input multiplexer arrangement for selecting a set of signals from the one of the TAP controllers that is enabled, an output multiplexer arrangement for feeding a TMS signal to the one of the TAP controllers that is enabled; and an output control circuit responsive to each of the multiple TAP controllers and to the TAP link module, the output control circuit configured and arranged to output one of the test signals respectively provided by the multiple TAP controllers.
Other aspects of the present invention are directed to alternative reset implementations for the TLM and TAP controllers, independent of the presence of a reset pin on each of the respective TAPs.
The above summary is not intended to provide an overview of all aspects of the present invention. Other aspects of the present invention are exemplified and described in connection with the detailed description.
REFERENCES:
patent: 5627842 (1997-05-01), Brown et al.
patent: 5708773 (1998-01-01), Jeppesen, III et al.
patent: 6073254 (2000-06-01), Whetsel
Whetsel, Lee, An IEEE 1149.1 Based Test Access Architecture For ICs With Embedded Cores, Texas Instruments.
IEEE Std 1149.1 (JTAG)Testability Primer, Texas Instruments, 1997 Semiconductor Group.
IEEE Std 1149.1-1990, IEEE Std Test Access Port and Boundary-Scan Architecture, IEEE Computer Society, Oct. 21, 1983.
Adusumilli Swaroop
Cassetti David
Steele James
Koninklijke Philips Electronics N.V. (KPENV)
Moise Emmanuel L.
LandOfFree
Method and arrangement for controlling multiple test access... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and arrangement for controlling multiple test access..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and arrangement for controlling multiple test access... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2840117