Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-08
2003-05-20
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C714S734000
Reexamination Certificate
active
06567942
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to an improved data processing system and in particular to a method and an apparatus for building self-test code on-chip for an array structure. Still more particularly, the present invention provides a method to enhance the functionality of the instruction array used to implement the testing algorithms.
DESCRIPTION OF THE RELATED ART
In general, integrated circuit arrays are tested by providing a known data input at a known address to the array and comparing the output of the array to the expected output. One well-known and widely used prior art system for testing integrated circuit logic is called Array Built-In Self Test (ABIST) technology. ABIST allows high speed testing of the array without having a large number of input/output connections to the chip itself. Key ingredients to this approach are to provide high speed testing and to confine the test system to a minimum area of the chip. In prior art systems, test patterns have generally been limited to a well-known set including all 0's, all 1's, checkerboard, checkerboard complement, and pseudo-random. These prior art systems permit very limited looping and addressing controls.
U.S. Pat. No. 5,633,877 to Shephard et al, issued May 27, 1997, provides a programmable ABIST function for VLSI logic or memory modules. This circuitry provided the provision of an array built-in self test system which allows self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. The test sequence is controlled by scanned logical test vectors (instructions), which can be changed, making the task of developing complex testing sequences relatively easy.
However, it is advantageous to be able to implement more complex ABIST algorithms in fewer programmable ABIST instructions thereby reducing the number of ABIST engine initializations and/or the depth of the ABIST instruction array, with only modest increases in circuit components on the chip.
SUMMARY OF THE INVENTION
A programmable array built-in self test system for testing an embedded array allows self test functions, e.g. test patterns, read/write access, and test sequences, to be modified without hardware changes to the test logic. Prior programmable ABIST systems have three types of control structure: scan only mode control bits; direct use of bits from the microcode instruction; and state machines that are controlled by microcode instructions which may then be used to provide feedback to the branch control functions that control the microcode instruction pointer.
The present invention discloses a fourth type of control structure that can be used to reduce the number and/or size of the microcode instructions that are required to implement many array test algorithms. This fourth type of control structure is used to modify the values that are generated by the original three array control structure types. This fourth control mechanism is implemented as a the test mode register in the preferred embodiment of this invention.
Two other improvements are made to control the looping mechanism. The first is the addition of a function which allows the branch pointer to be updated to point to the current instruction, thereby enabling branches to multiple places in the ABIST instruction set.
The second improvement is the addition of test mode compare latches and the test mode comparator which allow branches to be taken based on the state of the test mode register.
REFERENCES:
patent: 4835774 (1989-05-01), Ooshima et al.
patent: 5577050 (1996-11-01), Bair et al.
patent: 5633877 (1997-05-01), Shephard, III et al.
patent: 5796745 (1998-08-01), Adams et al.
Salys Casimer K.
Tu Christine T.
Walder, Jr. Stephen J.
Yee Duke W.
LandOfFree
Method and apparatus to reduce the size of programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus to reduce the size of programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus to reduce the size of programmable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3063291