Method and circuit for parametric testing of integrated...

Details Method and circuit for parametric testing of integrated... Method and circuit for parametric testing of integrated...

2007-06-12

2007-06-12

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S724000, C326S052000

Reexamination Certificate

active

11106743

ABSTRACT:
A circuit for parametric testing of an integrated circuit includes an integrated circuit having a plurality of input buffers and a plurality of XOR gates. The plurality of XOR gates have a first input that is connected to an output of one of the input buffers and having a second input that is connected to an output of a preceding XOR gate to form an XOR logic tree.

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patent: 2003/0115521 (2003-06-01), Rajski et al.
National Semiconductor, “PC87372 LPC SuperI/O with Glue Functions”, Oct. 2002, found at www.national.com or www.winbond.com. pp. 1, 21-22, 28-29 and 121.
Cirrus Logic, “CS4281 Programming Manual”, Mar. 2000, found at www.cirrus.com. pp. 1, 200 and 227.
Trident Microsystems, “Trident 4DWAVE-DX Technical Reference Manual”, Apr. 1998. pp. i-ii, iv and 30. Found at http://www.alsa-project.org/alsa/ftp/manuals/trident/4dwave—dx.pdf.

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