Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-10-09
2007-10-09
Louis-Jacques, Jacques (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S734000, C714S745000, C702S075000, C702S106000, C716S030000
Reexamination Certificate
active
10906481
ABSTRACT:
A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of the boundary scan cells; and means for characterizing signal propagation through each boundary scan segment.
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Gillis Pamela S.
Litten David D.
Oakland Steven F.
LeStrange Michael J.
Louis-Jacques Jacques
Schmeiser Olsen & Watts
Trimmings John P.
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