Method and circuit for scan testing latch based random...

Details Method and circuit for scan testing latch based random... Method and circuit for scan testing latch based random...

2006-12-19

2006-12-19

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

07152194

ABSTRACT:
A latch based random access memory includes an input data register; an input data buffer coupled to the input data register; a latch array coupled to the input data buffer; and a latch array bypass multiplexer for selecting one of the input data buffer and the latch array in response to a memory scan mode signal to generate a first data output of the latch based random access memory from the input data buffer during logic scan testing and a second data output of the latch based random access memory from the latch array during memory scan testing.

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patent: 6341092 (2002-01-01), Agrawal
patent: 6442092 (2002-08-01), Tomita
patent: 6698005 (2004-02-01), Lindkvist

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