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Test method and apparatus using energy consumption ratio

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method and architecture for circuits having inputs

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method and test apparatus for an electronic module

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test method and test circuit for electronic device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method and test circuit for electronic device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Test method and test device for electronic memories

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test method and test system for semiconductor device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test method for a semiconductor integrated circuit having a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method for data storage characteristics of memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test method for determining the wire configuration for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test method for guaranteeing full stuck-at-fault coverage of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test method for high speed semiconductor devices using a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test method for nonvolatile memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test method of cache memory of multiprocessor system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Utility Patent

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Test method of chips in a semiconductor wafer employing a test a

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Test method of semiconductor intergrated circuit and test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test methodology based on multiple skewed scan clocks

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Test mode circuit capable of surely resetting test mode signals

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Test mode circuit of semiconductor memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Test mode control circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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