Test method for nonvolatile memory

Details Test method for nonvolatile memory Test method for nonvolatile memory

2007-11-06

2007-11-06

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

11081636

ABSTRACT:
A control terminal section CON and an address terminal section ADDR of a test apparatus are respectively connected to those of a flash memory. A first to an (n−1) -th input and output terminal of the test apparatus are connected to data terminals of the flash memory. Further, an n-th and an (n+1)-th input and output terminal of the test apparatus are connected to a multifunctional terminal of the flash memory. The (n+1)-th input and output terminal is established as a dedicated terminal to receive data supplied to the test apparatus. The first to the n-th input and output terminal of the test apparatus are used to output the writing data to the flash memory, while the (n+1)-th input and output terminal is used to detect the completion signal output from the flash memory.

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patent: 6011720 (2000-01-01), Tanaka
patent: 6085281 (2000-07-01), Kopp et al.
patent: 6219289 (2001-04-01), Satoh et al.
patent: 2000-040389 (2000-02-01), None

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