Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-07-04
2006-07-04
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000, C365S201000
Reexamination Certificate
active
07073106
ABSTRACT:
A method, computer program product and system for testing stuck-at-faults. A first register may be loaded with a first value where the first value may be written into each entry in a memory array. A second register may be loaded with a second value. A third register may be loaded with either the second value or a third value. The second and third values are pre-selected to test selector circuits for stuck-at-faults with a pattern where the pattern includes a set of bits to be inputted to selector circuits and a set of bits to be stored in the memory cells. A value stored in the n-most significant bits in both the second and third registers may be predecoded to produce a predecode value. The predecode value may be compared with the value stored in the n-most significant bits in an entry in the memory array to determine a stuck-at-fault.
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Paredes Jose A.
Shephard, III Philip G.
Skergan Timothy M.
Vanderschaaf Neil R.
Chung Phung My
International Business Machines - Corporation
Salys Casimer K.
Voigt, Jr. Robert A.
Winstead Sechrest & Minick P.C.
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