Lab-on-chip system and method and apparatus for...
Lab-on-chip system and method and apparatus for...
Lane testing with variable mapping
Language processing system which generates debugging source file
Large-scale integrated circuit and method for testing a...
Last-in first-out data stacks and processing data using such...
Latch and phase synchronization circuit using same
Launch-on-shift support for on-chip-clocking
Layered decoding approach for low density parity check...
Layered decoding of low density parity check (LDPC) codes
Layered low density parity check decoding for digital...
Layered multiple description coding
Layered multiple description coding
Layered multiple description coding
Layout for a semiconductor memory device having redundant elemen
Layout for a semiconductor memory device having redundant...
Layout for semiconductor memory device having a plurality of...
Layout for semiconductor memory device wherein intercoupling lin
LBIST controller circuits, systems, and methods with...
LDPC (low density parity check) code size adjustment by...