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o,k,m,/m recording code

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Object reconstruction on object oriented data storage device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Observability register architecture for efficient production...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Obtaining cyclic redundancy code

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Off-pitch column redundancy using dynamic shifters

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Offset test pattern apparatus and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On chip data comparator with variable data and compare...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On chip debugging method of microcontrollers

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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On chip diagnosis block with mixed redundancy

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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On chip programmable data pattern generator for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On the fly write reallocation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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On-board FIFO memory module for high speed digital sourcing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-board testing circuit and method for improving testing of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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On-board testing circuit and method for improving testing of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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On-board testing circuit and method for improving testing of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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On-chip and at-speed tester for testing and characterization...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip and at-speed tester for testing and characterization...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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On-chip circuit and method for testing memory devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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On-chip circuit and method for testing memory devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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On-chip circuit for transition delay fault test pattern...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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