Test method of cache memory of multiprocessor system

Details Test method of cache memory of multiprocessor system Test method of cache memory of multiprocessor system

1998-05-28

2001-01-02

Tu, Trinh L. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S015000, C714S720000, C702S117000

Utility Patent

active

06170070

ABSTRACT:

CLAIM FOR PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. § 119 from an application for TEST METHOD OF CACHE MEMORY OF MULTIPROCESSOR SYSTEM earlier filed in the Korean Industrial Property Office on the 28
th
of May 1997, and there duly assigned Ser. No. 21336/1997, a copy of which application is annexed hereto.
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a cache memory test method, and more particularly, to a test method for cache memories disposed between processors and a shared memory accessed via a bus, in a multiprocessor system in which each of the processors has a cache memory.
2. Related Art
Generally, a multiprocessor system using a plurality of processors with respective cache memory connected via a system bus for accessing a shared memory via the system bus in order to attain high performance and reduce bus traffic. Exemplars of such contemporary multiprocessor systems are disclosed in U.S. Pat. No. 5,247,649 for Multi-Processor System Having A Multi-Port Cache Memory issued to Bandoh, U.S. Pat. No. 5,493,668 for Multiple Processor System Having Software For Selecting Shared Cache Entries Of An Associated Castout Class For Transfer To A DASD With One I/O Operation issued to Elko et al., U.S. Pat. No. 5,623,626 for Logical Cache Memory For Multi-Processor System issued to Morioka et al., U.S. Pat. No. 5,634,027 for Cache Memory System For Multiple Processors With Collectively Arranged Cache Tag Memories issued to Saito, and U.S. Pat. No. 5,666,513 for Automatic Reconfiguration Of Multiple-Way Cache System Allowing Uninterrupted Continuing Processor Operation issued to Whittaker.
As the number of processors accessing a system bus increases, competition for the right to use the system bus increases. Likewise, as the processing speed of processors increases, the difference in the processing speeds between the processors and the system bus increases. Therefore, a cache memory of high speed is typically included in each processor of the multiprocessor system. The cache memory is a hardware resource disposed between the processor and the shared memory for temporarily storing data obtained from the shared memory. The access speed of the cache memory must be high. Accordingly, the processor need not always access the shared memory through the system bus, and the use of the cache memory reduces the competition for the right to use the system bus and increases the use efficiency of the system bus. In a multiprocessor system for performing various programs, the cache memory of the respective processor also stores data shared between the processors. Consequently, modification of data in the cache memory must be informed to other processors, such that data consistency of the cache memories is maintained.
For example, if data of the shared memory is to be stored in the cache memory, the processor must first modify the data and observe whether other processors require the modified data. If another processor requires the modified data, the processor having modified the data must prevent other processors from accessing the shared memory, and then write the modified data to the shared memory, before allowing other processors to access the shared memory. Maintaining data consistency of the cache memory requires elaboration and stable operation. Therefore, it is very important in aspects of system stabilization and development period reduction to effectively and rigorously test the cache memory.
A test program is generally stored in the shared memory for testing the cache memory. Examples of contemporary testing techniques for the cache memory are disclosed in U.S. Pat. No. 5,073,891 for Method And Apparatus For Testing Memory issued to Patel, U.S. Pat. No. 5,165,029 for Cache Memory With Test Function issued to Sawai et al., U.S. Pat. No. 5,586,279 for Data Processing System And Method For Testing A Data Processor Having A Cache Memory issued to Pardo et al., U.S. Pat. No. 5,592,616 for Method For Performing Efficient Memory Testing On Large Memory Arrays Using Test Code Executed From Cache Memory issued to Finch et al., U.S. Pat. No. 5,638,382 for Built-In Self Test Function For A Processor Including Intermediate Test Results issued to Krick et al., and U.S. Pat. No. 5,671,231 for Method And Apparatus For Performing Cache Snoop Testing On A Cache System issued to Cooper. Generally, the test program for testing the cache memory is first read from the shared memory and stored in a certain code region of the cache memory. Then, the test program is executed to test the cache memory. At this time, while the test program is executed, data may be written to the code region of the cache memory where the test program is stored, to thereby flush the test program. In order to repeatedly test the cache memory, the processor must read out the test program of the shared memory which extends the time for testing the cache memory. In addition, additional load is required for hardware logic to maintain data consistency of the cache memory, if the cache memory test is reliable.
SUMMARY OF THE INVENTION
Accordingly, it is therefore an object of the present invention to provide a multiprocessor system comprising a plurality of processors provided with a test function for testing a cache memory.
It is also an object to provide a test method for effectively testing a cache memory of a multiprocessor system having a shared memory accessed via a system bus.
These and other objects of the present invention can be achieved by a test method for a cache memory of a multiprocessor system having a plurality of processor modules and a shared memory accessed via a bus with each processor module acting as a master of the bus and having a cache module. The test method includes dividing the cache memory into a test region, to be tested, and a code region, to store a test program; positioning the test program from the shared memory at a corresponding code region of the cache memory; and reading the test program stored in the shared memory and writing the test program in the code region of the cache memory to perform the testing of the cache memory.
The test program includes a program executing module for initiating the cache memory test, and a test program module satisfying protocol for maintaining data consistency of the cache memory and for generating a bus cycle such that the maximum load is placed on hardware between the cache memory and the shared memory according to a state of the cache memory, to test the cache memory. In addition, the test program further comprises a synchronization module for determining the number of processor modules participating in the cache memory test and synchronizing the processor modules to add heavy load to the cache memory, and an error process module for storing and controlling error information when errors occur during the cache memory test.
Preferably, in the case that modules ‘RQ’ each acting as a bus master of the multiprocessor system have predetermined series of numbers, the synchronization performed by the synchronization module comprises the steps of: initializing a sync-flag value stored in the shared memory; setting the sync-flag value according to the number of modules ‘RQ’ acting as bus masters of the multiprocessor system, and determining whether the sync-flag value is equal to the assigned number of the modules ‘RQ’, and if so, reducing the sync-flag value by a predetermined value, and if not, checking the sync-flag value until the sync-flag value equal to an initial value.
The present invention is more specifically described in the following paragraphs by reference to the drawings attached only by way of example.


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patent: 535

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