Test method and test system for semiconductor device

Details Test method and test system for semiconductor device Test method and test system for semiconductor device

2006-03-14

2006-03-14

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

07013414

ABSTRACT:
Method and system for shortening the time needed to test a semiconductor device having a plurality of memory circuits. The semiconductor device includes an address decoder for selecting a plurality of memory circuits and causing the memory circuits to perform a read/write operation. A comparator receives plural pieces of read data read from the plurality of memory circuits and compares the plural pieces of read data with one another. A processing unit compares one of the plural pieces of read data with write data. Using the comparison results of the comparator and the processing unit shorten the time needed to test the plurality of memory circuits.

REFERENCES:
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patent: 6480979 (2002-11-01), Tomari
patent: 6546511 (2003-04-01), Sim et al.
patent: 6550023 (2003-04-01), Brauch et al.
“Processor-Programmable Memory BIST for Bus-connected Embedded Memories” Tsai et al. Design Automation Conference Proceedings, 2001. Publication Date: Jan. 30-Feb. 2 2001 pp. 325-330 Inspec Accession No.: 6924510.

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