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Connection matrix for a microcontroller emulation chip

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Connection of auxiliary circuitry to tap and instruction...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Connection of auxiliary circuitry to tap and instruction...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Context save and restore using test scan chains

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Continuous application and decompression of test patterns to...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Continuous application and decompression of test patterns to...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Control circuit for releasing residual charges

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Control register bus access through a standardized test access p

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Control signal synchronization of a scannable storage circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Controller for scan distributor and controller architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Controller receiving combined TMS/TDI and suppyling separate...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Controller receiving combined TMS/TDI and suppyling separate...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Controlling the content of specific desired memory elements...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Conversion device, conversion method, program, and recording...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Conversion device, conversion method, program, and recording...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Core circuit test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Core test circuits controlling boundary and general external...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Cost-based performance driven legalization technique for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Coverage circuit for performance counter

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Coverage decoder circuit for performance counter

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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