Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-09-25
2007-09-25
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S047300
Reexamination Certificate
active
10635372
ABSTRACT:
Circuitry for use with a general purpose performance counter (“GPPC”) connected to a bus carrying a plurality of encoded state coverage signals indicative of test coverage in a logic design, wherein the circuitry is operable to decode and capture the encoded coverage information. A selection circuit associated with the GPPC is operable to select the encoded state coverage signals from a multi-bit event signal on the bus. A line decoder coupled to the selection circuit decodes the encoded state coverage signals into N one-hot signals, which are asserted based on coverage of corresponding states during test. A capture circuit is operable to capture the N one-hot signals for further processing.
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Hewlett--Packard Development Company, L.P.
Kerveros James C
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