Conversion device, conversion method, program, and recording...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S741000, C714S728000, C714S729000, C714S030000, C714S724000, C714S739000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

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08037387

ABSTRACT:
Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test pattern100agiven in advance for a logic circuit into an intermediate test pattern100bof a bit constitution of different logic values, where the constitution elements of the initial test pattern100aare at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test pattern100awhich meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.

REFERENCES:
patent: 6968286 (2005-11-01), Watkins
patent: 7225378 (2007-05-01), Ishida et al.
patent: 7685491 (2010-03-01), Lin et al.
patent: 2006/0041810 (2006-02-01), Ishida et al.
patent: 2007/0016836 (2007-01-01), Rajski et al.
patent: 2009/0183041 (2009-07-01), Rajski et al.
patent: 2010/0146350 (2010-06-01), Lin et al.
patent: 2001-04710 (2001-01-01), None
International Search Report for PCT/JP2007/062929 dated Aug. 28, 2007.

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