Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-04-27
2009-06-02
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S731000, C327S202000
Reexamination Certificate
active
07543205
ABSTRACT:
A system of control signal synchronization of a scannable storage circuit includes any number of storage circuits interconnected together with logic circuitry to form at least a portion of a functional circuit. Each of the storage circuits may include an input transmission gate to apply any one of a data input and a scan input to a storage element of the storage circuit based on an input circuitry that considers the state of the scan enable signal and a timing signal of a clock associated with the storage element. In addition, a control signal in a master latch of the storage element may synchronously close a hold loop in the master latch when the input transmission gate is opened upon the timing signal of the clock transitioning to a different state.
REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 5068603 (1991-11-01), Mahoney
patent: 5719878 (1998-02-01), Yu et al.
patent: 5926487 (1999-07-01), Chappell et al.
patent: 2006/0095819 (2006-05-01), Bhatia
Lines, Andrew;Asynchronous Interconnect for Synchronous SoC Design; Micro, IEEE (online), vol. 24, No. 1, pp. 32-41. Pub. Feb. 2004 (retrieved Jul. 10, 2008)—Cited in Foreign Search Rpt.
Brady III Wade James
Britt Cynthia
Stephens Dawn V.
Tabone, Jr. John J
Telecky , Jr. Frederick J.
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