Control register bus access through a standardized test access p

Details Control register bus access through a standardized test access p Control register bus access through a standardized test access p

1995-05-02

2000-04-25

Tu, Christine Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060556560

ABSTRACT:
A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.

REFERENCES:
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5448576 (1995-09-01), Russell
patent: 5459737 (1995-10-01), Andrews
"IEEE Standard Test Access Port and Boundary-Scan Architecture", IEEE, May 21, 1990. IEEE Std 1149.1 -1990.
"Pentium.TM. Family User's Manual" vol. 1: Data Book, Intel Corporation, 1994 pp. 11-1 to 11-14.

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