Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-06-28
2011-06-28
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
07971118
ABSTRACT:
Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device converts a test vector set corresponding to the full scan sequential circuit. The conversion device comprises a setting unit for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit.
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Date Hiroshi
Kajihara Seiji
Minamoto Yoshihiro
Miyase Kohei
Wen Xiaoqing
Gaffin Jeffrey A
Japan Science & Technology Agency
Kyushu Institute of Technology
Nguyen Steve
Rankin , Hill & Clark LLP
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