Coverage circuit for performance counter

Details Coverage circuit for performance counter Coverage circuit for performance counter

2003-08-06

2008-08-19

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S047300, C714S733000

Reexamination Certificate

active

07415643

ABSTRACT:
A coverage circuit for use with a general purpose performance counter (“GPPC”) connected to a bus for capturing test coverage information encoded as N one-hot signals indicative of coverage in a logic design. An OR logic block is included for bit-wise ORing the N one-hot signals with a N-bit mask value stored in a register block so that an N-bit output may be generated by the OR logic block depending on the logic transitions of the one-hot signals. A Multiplexer (MUX) block is provided for selecting the N-bit output from the OR logic block under control of at least one control signal, wherein the N-bit output is operable to be stored into the register block when selected by the MUX block.

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