Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-04-18
2009-12-22
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S701000, C716S030000, C716S030000
Reexamination Certificate
active
07636876
ABSTRACT:
A method of placing a circuit design can include selecting one or more candidate mobile nodes from a plurality of overlapped nodes of the circuit design and determining a gain region for each candidate mobile node. The method also can include assigning the candidate mobile node to a site within a gain region according to a cost function. The gain region is associated with the candidate mobile node. The method further can include iteratively selecting and assigning candidate mobile nodes according to a measure of overlap for the circuit design.
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Dasasathyan Srinivasan
Srinivasan Sankaranarayanan
Chung Phung M
Cuenot Kevin T.
Hardaway Michael R.
Xilinx , Inc.
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