Scanning device and method for hierarchically forming a scan pat
Scheduling the concurrent testing of multiple cores embedded...
Secure scan design
Secure software system and related techniques
Segmented addressable scan architecture and method for...
Segmented algorithmic pattern generator
Segmented algorithmic pattern generator
Segmented compaction with pruning and critical fault...
Segmented scan chains with dynamic reconfigurations
Select and enable leads connecting IC taps and embedded...
Selectable JTAG or trace access with data store and output
Selectable JTAG or trace access with data store and output
Selectable sense amplifier delay circuit and method
Selecting a scan topology
Selecting between tap/scan with instructions and lock out...
Selecting different 1149.1 TAP domains from update-IR state
Selecting test circuitry from header signals on power lead
Selective control of test-access ports in integrated circuits
Selective control of test-access ports in integrated circuits
Selectively accessing test access ports in a multiple test...