Selectable sense amplifier delay circuit and method

Details Selectable sense amplifier delay circuit and method Selectable sense amplifier delay circuit and method

1998-11-16

2001-07-31

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C365S201000, C365S194000

Reexamination Certificate

active

06269462

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and to a method of designing the semiconductor device. More particularly, the present invention relates to a semiconductor device equipped with a sense amplifier which becomes operative when receiving a read enable signal, and to a method of designing the semiconductor device.
2. Description of the Background Art
There has been known a semiconductor device, e.g., a memory IC, equipped with a sense amplifier which becomes operative when receiving a read enable signal.
FIG. 9
is a circuit diagram showing a sense amplifier
10
and other elements provided for the existing semiconductor device. The sense amplifier
10
has a Data terminal
12
and a /Data terminal
14
. The Data terminal
12
and the /Data terminal
14
are connected to an unillustrated Data line and an unillustrated /Data line, respectively. The Data line and the /Data line are transmission lines each of which receives Data or /Data signal from a corresponding memory cell when the address of the memory cell is designated.
The sense amplifier
10
has an output terminal
16
and an enable terminal
18
. The sense amplifier is a differential amplifier which amplifies a voltage across the Data terminal
12
and the /Data terminal
14
and outputs the thus-amplified voltage from the output terminal
16
when receiving a read enable signal at the enable terminal
18
. The enable terminal
18
of the sense amplifier
10
is connected to a delay circuit
20
formed from a plurality of inverter circuits connected in series.
FIGS. 10A and 10B
are timing charts for explaining the operation of the delay circuit
20
.
FIG. 10A
shows a waveform of the read enable signal supplied to the delay circuit
20
from an internal circuit of the semiconductor device. In contrast,
FIG. 10B
shows a waveform appearing at a node A shown in
FIG. 9
, i.e., the enable terminal
18
of the sense amplifier
10
.
As shown in
FIGS. 10A and 10B
the delay circuit
20
supplies a read enable signal produced by the internal circuit of the semiconductor device to the enable terminal
18
of the sense amplifier
10
after a lapse of a predetermined delay time T. Accordingly, the sense amplifier
10
commences to amplify the Data signal when the predetermined delay time T has elapsed after the internal circuit of the semiconductor device has changed the enable signal from a low state to a high state.
In a semiconductor device, a certain length of time is required for the Data signal issued from the memory cell to reach the sense amplifier
10
after designation of an address of the memory cell from which data are to be output. The existing semiconductor device reliably performs the amplifying function consuming a small amount of power when the delay time T of the delay circuit
20
matches a propagation time of the Data signal. Therefore, there is desired that the delay circuit
20
is provided so as to meet the aforementioned conditions.
As shown in
FIG. 9
, the existing semiconductor device has a backup delay circuit
22
provided in a circuit board in order to satisfy the aforementioned requirements. If the sense amplifier
10
is not enabled at a desired timing; namely, if the delay time T generated by the delay circuit
20
is not a desired time, the circuit for propagating the read enable signal is changed to the backup delay circuit
22
by changing a mask used for forming an aluminum wiring layer or a through hole. In the existing semiconductor device, the desired delay time T is ensured by changing the circuit configuration by trial and error under the previously-described method.
However, according to the existing method, it is required to make different prototype circuits by replacing masks over and over again until the configuration of the delay circuit is determined. Consequently, a large cost and much time are required to determine the circuit configuration when the existing method is used in a designing phase of the semiconductor device.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a novel and useful semiconductor device, and a novel and useful method of designing the semiconductor.
A more specific object of the present invention is to provide a semiconductor device capable of readily setting a delay time after an elapse of which a sense amplifier is enabled to an appropriate time, as well as a method of designing the semiconductor device.
The above object of the present invention is achieved by a semiconductor device. The semiconductor device includes a sense amplifier which becomes able to amplify a signal when receiving a read enable signal; a delay unit which can provide a plurality of transmission paths having different delay times and which propagates the read enable signal through a transmission path corresponding to a selection signal among the plurality of transmission paths; a selection signal generation circuit capable of generating the plurality of selection signals; and a JTAG boundary scan test circuit which brings the selection signal generation circuit into operation when receiving a instruction.
The above object of the present invention is also achieved by a method of designing a semiconductor device having a sense amplifier which becomes able to amplify a signal when receiving a read enable signal. The method includes the steps of: providing a delay unit capable of formation of a plurality of transmission paths having different delay times and propagating the read enable signal through a transmission path corresponding to a selection signal among the plurality of transmission paths; providing a selection signal generation circuit capable of producing a plurality of selection signals; providing a JTAG boundary scan test circuit which brings the selection signal generation circuit into operation when receiving a instruction; and determining an optimum transmission path having an optimum delay time by evaluating the transmission path selected in accordance with an instruction from the JTAG boundary scan test circuit.
Further object of the present invention is to provide a semiconductor device capable of readily changing a delay time after a elapse of which a sense amplifier is enabled, and capable of readily testing the operation thereof while the sense amplifier is kept in reliably operative.
The above object of the present invention is achieved by a semiconductor device. The semiconductor device includes a sense amplifier which becomes able to amplify a signal when receiving a read enable signal; a delay unit which can provide a plurality of transmission paths having different delay times and which propagates the read enable signal through a transmission path corresponding to a selection signal among the plurality of transmission paths; and an instruction signal generation circuit which supplies to the delay unit, as the instruction signal, an OR result of addition of a predetermined maximum delay instruction signal output for the purpose of taking a transmission path having the maximum delay time as a transmission path for the read enable signal, and an arbitrary selection signal output for the purpose of choosing an arbitrary transmission path as a transmission path for the read enable signal.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.


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patent: 5204559 (1993-04-01), Deyhimy et al.
patent: 5305265 (1994-04-01), Shgibayashi
patent: 5430681 (1995-07-01), Sugawara et al.
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patent: 5602855 (1997-02-01), Whetsel, Jr.
patent: 5852617 (1998-12-01), Mote, Jr.
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patent: 0 511 752 A1 (1992-11-01), None
patent: 63-244494 (1988-10-01), None

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