Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-03
2002-10-15
Chung, Phung M. (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
06467058
ABSTRACT:
I. DESCRIPTION OF THE INVENTION
IA. Field of the Invention
The present invention is related to segmented compaction of vectors for testing sequential circuits using pruning and critical fault elimination. The present invention is embodied in methods for segmented compaction of vectors; in a system for compacting test vectors and a computer program product enabling a computer to perform segmented compaction.
IB. Background of the Invention
Circuits are tested using test sets comprising test vectors. During testing, a tester applies the test vectors in the test set to the circuit. The outputs generated by the circuit are studied to determine if certain faults exist in the circuit. As can be readily seen, the cost of testing sequential circuits is directly proportional to the number of test vectors in the test set. This is because, more the number of test vectors more is the cost of testing in terms of time and resources required. Therefore, short test sequences are desirable. Reduction in test set size can be achieved using static or dynamic test set compaction algorithms.
Several static compaction approaches for sequential circuits have been proposed. See T. M. Niermann, R. K. Roy, J. H. Patel, and J. A. Abraham, “Test compaction for sequential circuits,”
IEEE Trans. Computer-Aided Design
, vol. 11, no. 2, pp. 260-267, February 1992, B. So, “Time-efficient automatic test pattern generation system,” Ph.D. Thesis, EE Dept., Univ. of Wisconsin at Madison, 1994; I. Pomeranz and S. M. Reddy, “On static compaction of test sequences for synchronous sequential circuits,”
Proc. Design Automation Conf
, pp. 215-220, Jun. 1996; M. S. Hsiao, E. M. Rudnick, and J. H. Patel, “Fast algorithms for static compaction of sequential circuit test vectors,” Proc.
IEEE VLSI Test Symp
., pp. 188-195, April 1995; M. S. Hsiao and S. T. Chakradhar, “State relaxation based subsequence removal for fast static compaction in sequential circuits”, in
Proceedings, Design, Automation and Test in Europe
(
DATE
), February, 1998; and R. Guo, I. Pomeranz and S. M. Reddy, “Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration”, in
Proceedings, Design, Automation and Test in Europe
(
DATE
), February, 1998.
Some of these approaches cannot reduce test sets produced by random or simulation-based test generators. The reasons for this can be found in T. M. Niermann, R. K. Roy, J. H. Patel, and J. A. Abraham, “Test compaction for sequential circuits,”
IEEE Trans. Computer-Aided Design
, vol. 11, no. 2, pp. 260-267, February 1992; and B. So, “Time-efficient automatic test pattern generation system,” Ph.D. Thesis, EE Dept., Univ. of Wisconsin at Madison, 1994.
Static compaction techniques based on vector insertion, omission, and selection have already been investigated. For details, see I. Pomeranz and S. M. Reddy, “On static compaction of test sequences for synchronous sequential circuits,”
Proc. Design Automation Conf
, pp. 215-220, June 1996. The above mentioned static compaction techniques require multiple fault simulation passes. If a vector is omitted or swapped, the fault simulator is invoked. This is done to ensure that the fault coverage is not affected. Fault coverage is the number of faults detected by a specific test set. Though the above mentioned static compaction techniques produce very good compaction, they are computationally intensive.
Vector restoration techniques are aimed at restoring sufficient vectors necessary to detect all faults, starting with the harder faults. Fast static test set compaction based on removing recurring subsequences that start and end on the same states has also been reported recently. For details, see R. Guo, I. Pomeranz and S. M. Reddy, “Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration”, in
Proceedings, Design, Automation and Test in Europe
(
DATE
), February, 1998 and M. S. Hsiao, E. M. Rudnick, and J. H. Patel, “Fast algorithms for static compaction of sequential circuit test vectors,”
Proc. IEEE VLSI Test Symp
., pp. 188-195, April 1995. However, these test sets are not as compact as those achieved by algorithms that use multiple fault simulation passes. Recently, compaction based on vector reordering has also been proposed. For details, see M. S. Hsiao and S. T. Chakradhar, “State relaxation based subsequence removal for fast static compaction in sequential circuits”, in
Proceedings, Design, Automation and Test in Europe
(
DATE
), February, 1998. However, run-times using the vector reordering approach for large industrial designs are prohibitive.
Dynamic techniques perform compaction concurrently with the test generation process. Details on dynamic compaction techniques can be found in I. Pomeranz and S. M. Reddy, “Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques,” in
Proc. Fault
-
Tolerant Computing Symp
., pp. 53-61, June 1996; S. T. Chakradhar and A. Raghunathan, “Bottleneck removal algorithm for dynamic compaction in sequential circuits,”
IEEE Trans. on Computer-Aided Design
, (Accepted for publication) 1997, E. M. Rudnick and Janak H. Patel “Simulation-based techniques for dynamic test sequence compaction,”
Proc. Intl. Conf. Computer-Aided Design
, pp. 67-73, November 1996; and T. J. Lambert and K. K. Saluja, “Methods for Dynamic Test Vector Compaction in Sequential Test Generation,” in
Proc. Int. Conf. on VLSI Design
, pp. 166-169, January 1996. However, these dynamic testing techniques often require modification of the test generator.
Static compaction techniques, on the other hand, are employed after the test generation process. Therefore, they are independent of the test generation algorithm and do not require modifications to the test generator. In addition, static compaction techniques can further reduce the size of test sets obtained after dynamic compaction.
Significant progress has been made in static compaction of test sets for sequential circuits. Static compaction methods have been discussed in detail in S. K. Bommu and S. I Chakradhar and K. B. Doreswamy, “Vector Restoration using Accelerated Validation and Refinement”, in
Proceedings, Asian Test Symposium
, December, 1998; R. Guo, 1. Pomeranz and S. M. Reddy, “Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration”, in
Proceedings, Design, Automation and Test in Europe
(
DATE
), February, 1998; S. K. Bommu and S. T. Chakradhar and K. B. Doreswamy, “Static test sequence compaction based on segment reordering and fast vector restoration”, in
Proceedings, International Test Conference
, October, 1998; and S. K. Bommu and S. T. Chakradhar and K. B. Doreswamy, “Static compaction using overlapped restoration and segment pruning”, in
Proceedings, International Conference on Computer Aided Design
, November, 1998.
However, better techniques are required to further improve the speed and quality of test set compaction.
II. SUMMARY OF THE INVENTION
Known static compaction algorithms typically compact a given test vector set so that the fault coverage is preserved. The test set is fault graded for a specific defect model (for example, stuck-at faults) to determine the fault coverage. During compaction, the chosen defect model is used to grade the compacted vector set. The present invention is a new approach for compacting vector sets for large production designs. The present invention approach is based at least on the following key observations:
(1) Test sets for production circuits safeguard against a variety of physical defects. Since all defects cannot be covered using a single defect model, test sets include tests generated using multiple defect models like stuck-at, delay, or bridging fault models. Therefore, it is unlikely that a marginal drop in fault coverage during compaction of tests generated for a single defect model will adversely affect the test quality of the overall test set.
(2) Fault coverage is an aggregate measure that can be preserved as long a
Bommu Surendra K.
Chakradhar Srimat T.
Doreswamy Kiran B.
Chung Phung M.
NEC USA Inc.
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