Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-04-03
2009-06-09
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S726000
Reexamination Certificate
active
07546503
ABSTRACT:
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits.
REFERENCES:
patent: 5606566 (1997-02-01), Whetsel
patent: 6311302 (2001-10-01), Cassetti et al.
patent: 6587981 (2003-07-01), Muradali et al.
patent: 6658614 (2003-12-01), Nagoya
Bassuk Lawrence J.
Brady W. James
Chung Phung M
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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