Secure scan design

Details Secure scan design Secure scan design

2011-06-21

2011-06-21

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

07966535

ABSTRACT:
A circuit configuration for testing integrated circuitry featuring a number of system scan flip flops wired in series and connected to the integrated circuitry for inputting test signals and receiving test data back. At the front and back ends of the system scan flip flops there is an input multiplexer and an output multiplexer, each with a control input tied to a comparator. The multiplexers isolate the test circuitry until a predetermined scan key is received. When the comparator receives a k-bit scan key it enables the multiplexer to pass test data to the system scan flip flops.

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