Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-09-12
2009-06-09
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
07546501
ABSTRACT:
The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.
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“Dual use of power lines for data communications in a system-on-chip environment” by Chung et al. Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on Publication Date: May 23-26, 2005 On pp. 3355-3358 vol. 4 ISBN: 0-7803-8834-8 INSPEC Accession No. 8615095.
Bassuk Lawrence J.
Brady W. James
Britt Cynthia
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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