Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-06
2009-02-10
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S728000, C714S735000, C714S739000
Reexamination Certificate
active
07490281
ABSTRACT:
A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in defining counter dimensions within each segment. Single vectors or vector group sequences may be defined at any point as well. The system allows the user control of the pattern generator to compensate for tool and/or device under test latency timing issues. Inputs may be combined and processed into one contiguous pattern of vectors which are definable by the user.
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Gottsche Amy J.
Theodoseau Philip
Canale Anthony J.
Greenblum & Bernstein P.L.C.
International Business Machines - Corporation
Louis-Jacques Jacques
Tabone, Jr. John J
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