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Microprocessor and method for detecting faults therein

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Microprocessor comprising signature means for detecting an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Microprocessor on-chip testing architecture and implementation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Microprocessor with trace module

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Microprocessor with trace module

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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MISR simulation tool for memory BIST application

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mode entry circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mode entry circuit and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mode selection based on special sequence of state machine...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Model train command protocol using front and back error bytes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Model-based process for translating test programs

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modeling custom scan flops in level sensitive scan design

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Models and technique for automated fault isolation of open...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modifying a test pattern to control power supply noise

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modifying circuit designs running from both edges of clock...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modular architecture for memory testing on event based test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modular re-useable bus architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Modular/re-configurable test platform

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Module based flexible semiconductor test system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Module level scan testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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