Module level scan testing

Details Module level scan testing Module level scan testing

1996-09-09

2000-06-20

Canney, Vincent P.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G06F 1100

Patent

active

060790407

ABSTRACT:
A design of logic circuitry to be tested is divided into one or more discrete logic modules usable in other designs of circuitry. An automated test pattern generator (ATPG) program and its tools are applied to the discrete module while not also being applied to the remainder of the logic circuitry, with the result that an ATPG pattern is provided for the module. When the module is reused in another design of logic circuitry, the ATPG pattern is also reusable in such other design.

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Williams, Thomas W., et al., "Design for Testability--A Survey", Proceedings of the IEEE, vol., 71, No. 1, Jan. 1983, pp. 98-112.

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