Microprocessor on-chip testing architecture and implementation

Details Microprocessor on-chip testing architecture and implementation Microprocessor on-chip testing architecture and implementation

2006-04-11

2006-04-11

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S738000

Reexamination Certificate

active

07028239

ABSTRACT:
A method and apparatus are presented for on-chip testing of circuits in testing channels. In an embodiment of the present invention, the system includes a weight selector that allows for a wide variety of weighting of test data that is to be supplied to the testing channels. For example, the weight selector may be used to weight all bits in all channels or individual bits in a particular channel. Clock control and diagnostic logic may also be provided to selectively supply scan, functional, and/or stop clock signals to the testing channels. Channel filtering logic may be also provided to mask output data from a selected testing channel as desired. The method and apparatus may provide improved testing performance and power savings.

REFERENCES:
patent: 5925144 (1999-07-01), Sebaa
patent: 5983380 (1999-11-01), Motika et al.
patent: 6184810 (2001-02-01), Burns
patent: 6349392 (2002-02-01), Swoboda et al.
patent: 6557129 (2003-04-01), Rajski et al.

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