Modeling custom scan flops in level sensitive scan design

Details Modeling custom scan flops in level sensitive scan design Modeling custom scan flops in level sensitive scan design

2006-05-02

2006-05-02

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07039843

ABSTRACT:
A system and method for testing an integrated circuit is provided. The illustrative embodiment provides a scan cell for use with automatic test pattern generation (ATPG). In the scan cell of the illustrative embodiment, a flip-flop is configured as a master storage element and a latch is configured as a slave storage element. During standard operating mode, the flip-flop and the latch operate as standard storage elements in the circuit. During a test mode, the flip-flop and the latch form a shift register for shifting test pattern data through the circuit to identify and detect any faults in the circuit design.

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