Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-05-20
2000-10-03
Myers, Paul R.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714 27, 714 30, G01R 1328
Patent
active
06128758&
ABSTRACT:
A modular reusable bus architecture enhances testability of an integrated computer system in which multiple modules communicate over a system bus. Under the modular reusable bus architecture, the system bus can be configured to operate in different operation modes. In one embodiment, the bus architecture provides a test mode for testing an individual module within the integrated computer system, separate from the other modules. In another embodiment, the bus architecture configures the system bus to provide access to configuration registers and memory units disposed within each module, otherwise inaccessible in normal system operation. The modular reusable architecture can support any types and any number of modules, including modules incorporating analog and digital circuitry, and modules operating under different clock domains.
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Hall Christopher
Muwafi Jumana
Sewal Rajat
Kwok Edward C.
Myers Paul R.
National Semiconductor Corporation
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