MISR simulation tool for memory BIST application

Details MISR simulation tool for memory BIST application MISR simulation tool for memory BIST application

2001-05-31

2004-01-20

Chung, Phung M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S741000

Reexamination Certificate

active

06681357

ABSTRACT:

BACKGROUND OF INVENTION
In order to make computer system testing accurate and effective, the design of a computer system often includes test functionality within one or more devices of the computer system itself. One type of such a test design involves a built-in self test (“BIST”) technique. Typically, a BIST technique allows for device testing to occur through built-in hardware features. An advantage of such a BIST technique is that a particular device can indicate directly and quickly its failure status during testing.
FIG. 1
shows a block diagram of a typical prior art BIST design (
10
). The BIST design (
10
) includes a test controller (also known in the art as “BIST controller”) (
12
) which performs managerial functions such as running a particular test, determining when the test is done, and checking the responses, i.e., the outputs, generated by that particular test. The test controller (
12
) is connected to a multiplexor stage (
14
) to which the test controller (
12
) indicates whether to pass regular data input values to an input of a circuit being tested (
16
) (also known in the art as “circuit under test”) or whether to pass values generated by a test pattern generator (
18
) the circuit being tested (
16
).
The test pattern generator (
18
), under the control of the test controller (
12
), is typically capable of generating multiple test pattern values to the circuit being tested (
16
) depending on the various types of tests that can be conducted for the BIST design (
10
). The circuit being tested (
16
) has both regular logic (
20
) and test logic (also known in the art as “scan logic”) (
22
), where the regular logic (
20
) is used for regular, i.e., normal, data operations and the test logic (
22
) is used to test the functionality of the regular logic (
20
) based on values provided to it by the test pattern generator (
18
).
The circuit being tested (
16
) generates regular outputs and test outputs, where the test outputs are fed into a output response analysis stage (
24
). The output response analysis stage (
24
) is typically used to monitor the test outputs and compare the test outputs with predicted, i.e., expected, output values to determine whether the circuit is functioning properly. The output response analysis stage (
24
) is connected to the test controller (
12
) so that the test controller (
12
) can both manage the output response analysis stage (
24
) and receive signals from the output response analysis stage (
24
) indicating to it whether or not a particular test has failed.
When implementing circuitry for a BIST design, such as the one described above with reference to
FIG. 1
, consideration must be given to how test responses are handled in the output response analysis stage. Generally, it is not feasible to store in a circuit all expected test responses, and thus, a typical solution is to reduce a circuit's test responses to relatively short sequences. The process of reducing test responses to relatively short sequences is called “data compaction” and the resulting shortened sequences are called “signatures.” After a signature is created, the signature is compared to a “golden” signature, where the golden signature represents the expected signature for a particular test.
In order to generate a signature of a circuit's test responses, a multiple input signature register (“MISR”) is commonly used. A MISR inputs test response values from a circuit being tested and compacts the test response values into a signature, which is then compared to the golden signature to determine whether the circuit has a fault.
FIG. 2
shows a multiple input signature register (
30
) in a BIST design. Essentially, the MISR (
30
) inputs a vector of test response values in parallel from a circuit being tested, integrates those values with a value of a current state of the MISR (
30
), and leaves the result in the MISR (
30
) for integration with the next vector of test response values. If any single test response value from the circuit turns out to be inaccurate due to a circuit fault, the state of the MISR (
30
) is adversely affected such that a final result—the “signature”—will not be the same as an expected result.
Specifically, the MISR (
30
) shown in
FIG. 2
includes a sequence of n exclusive-OR gates (
32
,
34
,
36
) that each output to a corresponding flip-flop (
38
,
40
,
42
), where n equals the number of flip-flops in the MISR (
30
). Further, each exclusive-OR gate (
32
,
34
,
36
) has an input connected to a corresponding test response value from a circuit being tested (
44
).
A characteristic polynomial of a MISR indicates which flip-flops in the MISR are subject to feedback. Feedback is often created in a MISR to increase the number of states that a MISR can transition through. For instance, in
FIG. 2
, FF
1
and FF
0
(
40
,
42
) could be subject to feedback by connecting a third input of the corresponding exclusive-OR gates (
34
,
36
) to an output of FF
0
(
42
) (shown by dotted lines in FIG.
2
). In this case, the characteristic polynomial for the MISR (
30
) would be x
n
+x
2
+x+1. Moreover, such feedback connections are often referred to in the art as “taps.”
Because a MISR should be capable of transitioning through a maximum number of states, the MISR is physically structured according to its particular n value. The characteristic polynomial of a MISR that generates the maximum length state sequence is called a “primitive polynomial.” For example, for a MISR with n=20, the maximum state sequence occurs when its characteristic polynomial is x
n
+x
3
+1, and thus, the primitive polynomial of the MISR is x
n
+x
3
+1.
In order to generate a golden signature to compare with an actual resulting signature of the MISR, a signature simulation tool (also known as “MISR simulation tool”) is often used during a BIST application. The signature simulation tool is typically implemented in software, and during a test, the signature simulation tool forms its own MISR in software, determines the states of the MISR based on the circuit configuration being tested, and generates a golden signature to determine whether the signature generated by the MISR in hardware is correct.
However, due to the various sizes, types, and complex configurations of memory circuits, e.g., memory arrays, signature simulation tools are prone to inaccuracies. In other words, a signature simulation tool that is effective for a circuit such as a flip-flop is generally not effective for a circuit such as a memory array.
SUMMARY OF INVENTION
According to one aspect, a method for generating a signature for a memory test application comprises opening a configuration file, reading information from the configuration file, selectively creating structures to store data for the memory test application, running a test algorithm on the selectively created structures according to the information read from the configuration file, and generating a signature dependent on a result of the test algorithm.
According to another aspect, a configuration file includes an address size, a data bus width, a data background, a size of a signature register, a primitive polynomial of the signature register, a number of memory banks, an initial value of the signature register, and/or a type of the a test algorithm to be used for a memory test application.
According to another aspect, a method for simulation a signature register for a memory test application comprises opening a configuration file, reading information from the configuration file, selectively creating structures to store data for the memory test application, wherein selectively creating structures is dependent on the information read from the configuration file, running a test algorithm on the selectively created structures according to the information read from the configuration file, and generating a signature in the signature register dependent on a result of the test algorithm.
According to another aspect, a software tool that generates a signature for a test of a memory dev

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