Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-03-16
2002-04-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
06370662
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to the design of digital integrated circuits, and more specifically to automatically modifying digital integrated circuit designs to use positive clock signal transitions when changing internal circuit logic states.
The use of integrated circuits is widespread and pervasive. Integrated circuits implement complex logic operations, and often do so through the use of an exceedingly large number of logic gates. A significant concern in the design and testing of integrated circuits is that the integrated circuit, often comprising well over one million logic gates, implements specified logic operations without error.
Ideally, every possible combination of inputs to an integrated circuit is applied when the integrated circuit is in every possible internal logic state, thus allowing every possible output of the circuit to be compared with the functional requirements of the circuit. However, even for a combinational circuit, which is a circuit in which the outputs of the circuit depend directly on the inputs to the circuit, and which thereby does not contain memory elements, the number of possible input combinations is sufficiently large that the test of the circuit becomes an non-deterministic polynomial (NP) hard problem, that is one that cannot be solved in polynomial time. For a sequential circuit, which is a circuit that contains internal memory and thus may have a number of internal logic states, the problem of testing every conceivable input combination in every combination of logic states of the circuit becomes even more intractable.
Further, testing of the circuit by manipulating the primary inputs and examining the primary outputs provides little information as to a location of a fault within the circuit. The knowledge that a certain combination of inputs to a circuit results in an incorrect combination of outputs from the circuit may be of little use in determining where in the circuit the error occurs.
One method known in the art of providing additional detail as to the internal operation of the circuit is to insert scan flip-flops into the circuit. Absent other circumstances or situations, some of which are described below, any flip-flop present in a circuit may be converted to a scan flip-flop. Scan flip-flops may be used either as control points for inserting values into the circuit, or observation points for observing the operation of the circuit. Observation points are generally tied together to form a scan chain, with the scan chain forming a register which may be shifted out to capture the state of a portion of the circuit. Moreover, through the use of scan flip-flops a circuit may be divided into a number of logic cones. Each logic cone comprises a portion of the circuit, with the apex of the cone being a scan flip-flop.
An integrated circuit may contain thousands of logic cones. Accordingly, manual test of even the logic cones is impractical. Often Automatic Test Pattern Generation (ATPG) techniques are used to analyze a circuit design under test and generate test patterns providing maximum fault coverage of the circuit. The use of ATPG programs allows for extensive testing of a circuit without producing a test of such size that execution of the test is impractical.
ATPG programs are generally more efficient providing test patterns for combinational circuits than for sequential circuits. Although sequential circuits may be tested by ATPG programs, the testing requires generally substantially more time and provides substantially less coverage of the circuit under test. Moreover, ATPG programs generally require that a circuit comprising the design under test meet certain requirements so that the ATPG program may properly generate test patterns. For example, many ATPG programs require that a combinational circuit have a scan chain that operates on a single edge, usually the positive edge, of a clock signal as viewed at the origin of the clock signal. Thus, design for test tools may automatically exclude from a scan chain flip-flops using a negative edge of a clock signal as viewed at the origin of the clock signal, which may result in significant loss of test coverage.
SUMMARY OF THE INVENTION
The present invention provides a method and system for modifying digital circuits to increase the number of flip-flops or other memory elements using a single edge of a clock signal as viewed from a clock signal source. Accordingly, according to the present invention the parity of the clock signal at the clock signal source is determined. The parity of the clock signal at the clock signal source provides information as to whether a flip-flop changes state on the positive or negative edge of the clock signal as viewed at the clock signal source or origin. The circuit is modified along a clock signal path to change the parity of the clock signal at the clock signal source. This preferably changes the parity of the clock signal at the clock signal source to increase the number of flip-flops utilizing a clock signal of a first parity as opposed to a second parity during testing of the circuit.
Many of the attendant features of this invention will be more readily appreciated as this game becomes better understood by references to the following detailed description considered in connection with the accompanying drawings.
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De'cady Albert
Lamarre Guy
S3 Incorporated
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