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Method of and program product for performing gate-level...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of and system for testing an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of automatic fault isolation in a programmable logic...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of automatic latch insertion for testing application...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of automatically generating new test programs for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of automatically generating schematic and waveform...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of automatically generating schematic and waveform...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of controlling a test mode of a circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of controlling a test mode of a circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of controlling a test mode of a circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of design for testability and method of test sequence...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of design for testability for integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of design for testability test sequence generation...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of design for testability, method of design for avoiding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of design for testability, test sequence generation...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of determining non-accessible device I/O pin speed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of dynamic on-chip digital integrated circuit testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of efficiently loading scan and non-scan memory elements

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of evaluating core based system-on-a-chip

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of evaluating core based system-on-a-chip (SoC) and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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