Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-05-20
2008-05-20
Tu, Christine T. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
10804371
ABSTRACT:
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.
REFERENCES:
patent: 4366393 (1982-12-01), Kasuya
patent: 4398146 (1983-08-01), Draheim et al.
patent: 5155704 (1992-10-01), Walther et al.
patent: 5168181 (1992-12-01), Baiocchi et al.
patent: 5245577 (1993-09-01), Duesman et al.
patent: 5408435 (1995-04-01), McClure et al.
patent: 5475640 (1995-12-01), Kersh, III et al.
patent: 5604756 (1997-02-01), Kawata
patent: 5615164 (1997-03-01), Kirihata et al.
patent: 5651123 (1997-07-01), Nakagawa et al.
patent: 5734661 (1998-03-01), Roberts et al.
patent: 5778004 (1998-07-01), Jennion et al.
patent: 5787096 (1998-07-01), Roberts et al.
patent: 5831997 (1998-11-01), Kodashiro
patent: 5935266 (1999-08-01), Thurnhofer et al.
patent: 5944845 (1999-08-01), Miller
patent: 5951703 (1999-09-01), Sprouse et al.
patent: 6061817 (2000-05-01), Jones et al.
patent: 6138258 (2000-10-01), Miller
patent: 6421800 (2002-07-01), Miller
patent: 6591386 (2003-07-01), Miller
Micro)n Technology, Inc.
TraskBritt
Tu Christine T.
LandOfFree
Method of controlling a test mode of a circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of controlling a test mode of a circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of controlling a test mode of a circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3947730