Method of efficiently loading scan and non-scan memory elements

Details Method of efficiently loading scan and non-scan memory elements Method of efficiently loading scan and non-scan memory elements

2003-08-07

2008-11-04

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

07447960

ABSTRACT:
The present invention provides a method and apparatus for efficiently loading values into scan and non-scan memory elements. First, the network used to distribute control signals to the memory elements is cleared. Second, the desired values are loaded into the scan memory elements. Third, the values from the scan memory elements are propagated to the non-scan memory elements.

REFERENCES:
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 6510534 (2003-01-01), Nadeau-Dostie et al.
patent: 2003/0115522 (2003-06-01), Nadeau-Dostie et al.
patent: 2003/0177428 (2003-09-01), Wakabayashi et al.
patent: 2003/0188278 (2003-10-01), Carrie

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