Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-12-17
2002-03-05
Lee, Thomas (Department: 2182)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000, C714S739000, C714S741000, C324S1540PB, 37, 37
Reexamination Certificate
active
06353904
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of testing integrated circuits. More specifically, the present invention relates to techniques for developing test programs for testing mixed-signal integrated circuits.
BACKGROUND OF THE INVENTION
In the design of electronic devices and systems, modern electronics engineers are increasingly reliant upon the use of computer-aided engineering (CAE) tools. Typically, using software design tools, an engineer can create a schematic diagram of the desired integrated circuit. Thereafter, the operations of the design are simulated on a computer using simulation software. If the simulation does not provide the desired results, the engineer may alter the schematic and re-run the simulation process. This process is repeated until the simulation demonstrates that the circuit is providing the desired results. Thereafter, circuit dies (chips) are fabricated from the design. With the assistance of these CAE tools, the production cycle of an integrated circuit design can be shortened.
Due to complications in the fabrication process and/or unforeseen design flaws, some fabricated chips may not meet the desired specifications. Therefore, chip testing must be performed before shipment to the customers. This testing process is typically carried out with the assistance of automated testing equipment (ATE). A number of different models of ATEs are commercially available from various manufacturers. Each model operates somewhat differently, and each has a specific format for test programs that will cause that particular model to execute different tests on a specific integrated circuit.
For digital integrated circuits designed with the aforementioned CAE tools, the process of preparing a test program is relatively straightforward. In many instances, test vectors used during the simulation phase of the design process can be used again by the ATEs. In order to conform to the specific requirements of specific ATEs, translator software programs have also been devised to convert the simulation test vectors into appropriate formats readable by the ATEs. For experienced quality-assurance engineers, test programs for a new digital integrated circuit can be prepared in several hours.
However, designing test programs for analog or mixed-signal integrated circuits is a much more involved process. Test engineers usually need to program from scratch for each new analog or mixed-signal integrated circuits. For example, in order to test the functionalities a digital-to-analog converter (DAC), it is often necessary to program the ATE to perform differential linearity error analysis, Fourier transforms, and signal-to-noise ratio analysis, etc. Programming an ATE to perform these complicated analyses is time-consuming and requires a high level of circuit testing skills. To fully test the functionalities of a complicated mixed-signal integrated circuit, a test program may contain more than 10,000 lines, and may take an experienced quality assurance engineer several months to complete. For novice engineers, the process can take more than six months.
In a highly competitive high-technology market, a prolonged testing process unnecessarily extends the product development cycle and increases development cost. Thus, what is needed is a method of assisting quality-assurance engineers in testing mixed-signal integrated circuits. What is further needed is a method of automatically generating test programs for testing analog and mixed-signal integrated circuits.
SUMMARY OF THE DISCLOSURE
In accordance with the present invention, a method of automatically generating a mixed-signal test program is provided. Particularly, the method according to one embodiment of the present invention is implemented in software in the form of two software processes. The first software process includes a test-block extraction process which allows a user to extract re-usable test data from pre-existing test programs. The extracted re-usable test data is then stored in a template library in the form of test-block templates. In one embodiment, the user only needs to provide the names of the interested cells and the corresponding pin designations to extract re-usable test data from pre-exisiting test programs.
According to the present embodiment, the second software process includes a test-block retargeting process which allows a user to use the re-usable test data stored in the template library for a new mixed-signal integrated circuit. In the present embodiment, the names of the analog cells used in a new mixed-signal integrated design are provided to the test-block retargeting process. The test-block retargeting process will then retrieve the test-block templates corresponding to the interested analog cells from the template library. The test-block retargeting process then generates the analog test-blocks for the interested analog cells. The analog test-blocks are then automatically merged with digital test-blocks, which may be obtained from logic simulation tools, to generate a new mixed-signal test program for the new mixed-signal integreated circuit design.
Embodiments of the present invention include the above and further include a method of automatically generating test programs comprising the steps of: providing to a computer system a source test program; extracting re-usable test data from the source test program; storing the re-usable test data in the form of an analog test-block template in a template library; retrieving the analog test-block template from the template library; mapping the re-usable test data to specific pins of a new mixed-signal integrated circuit design to generate an analog test-block for the new design; retrieving predetermined digital test vectors from a digital test vectors source; and combining the analog test-block and the predetermined digital test vectors to generate a test program for the new mixed-signal integrated circuit design.
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Lee Thomas
Peyton Tammara
VLSI Technology Inc.
Wagner , Murabito & Hao LLP
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