Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-01-21
2001-09-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C716S030000
Reexamination Certificate
active
06292915
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to design for testability and test sequence generation for integrated circuits (LSIs). More particularly, it relates to techniques to design for testability for an RTL circuit, that is, an integrated circuit designed at register transfer level (RTL).
A typical example of the conventional method of design for testability includes scan design. In the scan design, a flip-flop (FF) included in a logically designed LSI is replaced with a scan FF which can be externally directly controlled (scanned in) and observed (scanned out), so that a problem of a sequential circuit can be simplified into a problem of test pattern generation of a combinational circuit. Thus, test sequences can be easily generated (“Digital Systems Testing and Testable DESIGN, Chapter 9, Design For Testability”, 1990, published by Computer Science Press).
The conventional scan design includes full scan design in which all FFs are replaced with scan FFs and partial scan design in which merely FFs difficult to observe and control are replaced with scan FFs so as to overcome problems such as increase in hardware overhead occurring in the full scan design, both of which are executed mainly at gate level.
However, according to the conventional partial scan design at gate level, an operation timing of a gate level circuit generated through the logic synthesis can be harmfully affected by the scan design, so that a normal operation cannot be guaranteed. Therefore, re-design of the circuit is required, which can cause a problem that the design takes a long period of time.
As a countermeasure, partial scan design at register transfer level (RTL) with higher abstraction than the gate level is recently proposed.
For example, in an integrated circuit designed at RTL (i.e., an RTL circuit), registers to be made scannable (hereinafter referred to as scannable registers) are selected by using a testability measure or the like within a specified range of scan ratio (1995, ASPDAC (Asia and South Pacific Design Automation Conference), pp. 209-216, “Design For Testability Using Register Transfer level Partial Scan Selection”).
However, in the partial scan design at RTL, it is difficult to achieve high fault coverage at RTL. Specifically, in the RTL partial scan design, the fault coverage is to be increased as far as possible within the specified range of scan ratio, and therefore, it is necessary to repeat a series of procedures of selection of registers to replace with scan registers, logic synthesis, insertion of a scan path and test sequence generation until high fault coverage is achieved. Accordingly, the entire scan design requires a long period of time, resulting in disadvantageously increasing a cost for the design for testability.
SUMMARY OF THE INVENTION
The present invention provides a method of design for testability for modifying design of an integrated circuit at RTL so as to attain testability, by which high fault coverage can be guaranteed at RTL.
Also, the invention provides a method of test sequence generation for easily generating test sequences for a circuit having an easily testable circuit structure such as an RTL circuit whose design is modified to be easily testable by the method of design for testability.
Specifically, the method of design for testability of this invention for modifying design of an RTL circuit, that is, an integrated circuit designed at register transfer level, so as to attain testability after manufacture, comprises a first step of specifying an easily testable circuit structure; and a second step of selecting scannable registers among registers included in the RTL circuit so that the RTL circuit in test has the easily testable circuit structure specified in the first step in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input.
According to the method of design for testability, scannable registers are selected so that the RTL circuit has the easily testable circuit structure specified in the first step. Therefore, high fault coverage can be guaranteed in upper stage of design. Furthermore, since the design for testability is performed at RTL, re-design can be largely avoided, and time required for the design of an LSI can be shortened as compared with time conventionally required.
Also, the method of test sequence generation, of this invention, for an RTL circuit, that is, an integrated circuit designed at register transfer level, the RTL circuit having an acyclic structure or having a structure in which scannable registers are selected and an acyclic structure is attained in assuming a normal data input of a scannable register as a pseudo-primary output and a data output thereof as a pseudo-primary input, comprises a first step of converting the RTL circuit into a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit; a second step of generating test patterns for the timeframe expanded combinational circuit generated in the first step; and a third step of transforming the test patterns generated in the second step into test sequences for the sequential circuit on the basis of data on timeframes including each of primary inputs and pseudo-primary inputs of the timeframe expanded combinational circuit generated in the first step.
According to the method of test sequence generation, the RTL circuit is converted, in the first step, into the gate level timeframe expanded combinational circuit for which test patterns can be easily generated, the test patterns for a combinational circuit are generated for the timeframe expanded combinational circuit in the second step, and the test patterns are transformed into test sequences for a scannable sequential circuit in the third step. In this manner, the test sequences for the sequential circuit can be easily generated.
REFERENCES:
patent: 5513118 (1996-04-01), Dey et al.
patent: 5522063 (1996-05-01), Ashar et al.
patent: 5726996 (1998-03-01), Chakradhar et al.
patent: 6185721 (2001-02-01), Hosokawa
patent: 5-203708 (1993-08-01), None
Lejmi, S et al. (Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits; IEEE, Oct. 21-25, 1995).*
Lejmi, S et al. (Retiming for BIST-sequential circuits; IEEE, May 3, 1995).*
Boppana, V. et al. (Partial scan design based on state transition modeling; IEEE, Oct. 25, 1996).*
Kwang-Ting Cheng (Partial scan designs without using a separate scan clock ; IEEE, May 3, 1995).*
Chih-Chang Lin et al (Scan paths through functional logic; IEEE, May 5-8, 1996).*
Gupta et al.(Testability Properties of Acyclic Structures and Applications to Partial Scan Design; IEEE, Apr. 1992).*
Mourad (Digital Design with Minimal Number of Scan Flip-Flops; IEEE, Oct. 1996).*
Hosokawa, T., et al., “A Partial Scan Design Method Based on N-Fold Line-Up Structures” Proceedings Sixth Asian Test Symposium (AT'97) Akita, Japan Nov. 17-19, 1997, Instutute of Electrical and Electronics Engineers, pp. 306-311.
A. Kunzmann, et al., An Analytical Approach to the Partial Scan Problem:, Journal of Electronic Testing: Theory and Applications, 1, pp. 163-174, 1990.
A. Motohara, et al., “A State Traversal Algorithm Using A State Covariance Matrix”, Proc. of 30th AMC/IEEE Design Automation Conference, pp. 97-101, 1993.
R. Gupta, et al., Partial Scan Design of Register-Transfer Level Circuits:, Journal of Electronic Testing: Theory and Applications, 7, pp. 25-46, 1995.
A. Motohara, et al., “Design for Testability Using Register Transfer Level Partial Scan Selection”, Proc. of Asia and South pacific Design Automation Conference, pp. 209-215, 1995.
T. Inoue et al., “An RT Level Partial Scan Design Method Based on Combinational ATPG”, Technical Report of the Institute of Electronics, Informantion and Communication Engineers, vol. 96, No. 519, pp. 73-80, Feb. 13, 1997.
H. Fujiwara et al., “Sequential Circuit Structure With Combinational Test Generation Complexity and its Application”, The Transactions of the Institute of Electronics, Information and Communi
Fujiwara Hideo
Hosokawa Toshinori
Inoue Tomoo
De'cady Albert
Lamarre Guy
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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