Method of design for testability for integrated circuits

Details Method of design for testability for integrated circuits Method of design for testability for integrated circuits

1999-06-04

2003-01-21

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06510535

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of design for testability for integrated circuits.
The scan design method is one of the conventional typical methods of design for testability. In the scan design method, a flip-flop (FF) included in a logically designed integrated circuit is replaced with a scan FF that can be externally directly controlled (scanned in) and observed (scanned out), and the scan FF is dealt with as a primary input/output. Thus, test sequences can be easily generated (“Digital Systems Testing and Testable DESIGN, Chapter 9: Design for Testability”, 1990, published by Computer Science Press).
The scan design is classified into two types: full scan design method in which all the FFs in a circuit are replaced with scan FFs; and partial scan design method in which part of FFs in a circuit are replaced with scan FFs. The full scan design method has disadvantages of a large area, low speed and high power consumption derived from addition of a test circuit, and these disadvantages can be reduced by the partial scan design method. A scan FF identification method usable in the partial scan design is described in detail in “An Exact Algorithm for Selecting Partial Scan Flipflop” (1994, DAC (Design Automation Conference), pp. 81-86) and its reference paper.
Also, a technique to identify scan FFs so that an integrated circuit can have an n-fold line-up structure has already been proposed (“A partial scan design method based on n-fold line up structures”, 1997, 6th Asian Test Symposium, pp. 306-311). An “n-fold line-up structure” is a structure for easing generation of test sequences for faults (see, for example, Japanese Laid-Open Patent Publication No. 10-124562). When scan FFs are identified so that an integrated circuit can have an n-fold line-up structure, high fault efficiency that cannot be achieved by the conventional partial scan design can be achieved.
FIG. 51
is a flowchart for showing procedures in identifying scan FFs so that an integrated circuit can have an n-fold line-up structure. First, all FFs are replaced with scan FFs (SJ
3
), thereby forming a so-called full scan circuit. It is then determined whether or not the circuit has an n-fold line-up structure when a given scan FF is replaced with a non-scan FF. When the circuit has an n-fold line-up structure, the FF is identified as a non-scan FF, and when not, the FF is identified as a scan FF (SJ
5
through SJ
7
). Such procedures are executed on all the FFs not having self loops (SJ
4
).
However, in the conventional algorithm, scan FFs are identified so that an integrated circuit can have an n-fold line-up structure, but the scan ratio of the integrated circuit resulting from the identification is not considered. Therefore, as a result of the method of design for testability, the scan ratio can be unnecessarily increased. When the scan ratio is increased, the area of a test circuit to be added to the integrated circuit is increased, resulting in reducing the advantages of the partial scan method.
Also, in accordance with examination made by the present inventor, it is found that the scan ratio of an integrated circuit and difficulty in generating test sequences can be largely varied depending upon the order of FFs subjected to the scan FF identification in the conventional algorithm.
SUMMARY OF THE INVENTION
An object of the invention is achieving higher fault efficiency in a method of design for testability using scan FF or register identification.
Specifically, the method of design for testability of this invention for modifying design of an integrated circuit designed at gate level or register transfer level, in order to attain testability after manufacture, comprises a full scan process for temporarily determining about all flip-flops (FFs) or registers in the integrated circuit to replace with scan FFs or registers; a sorting process for sorting the FFs or registers in accordance with a predetermined evaluation function indicating a degree of relation with difficulty in generating test sequences; and a non-scan selecting process for examining for each of the FFs or registers temporarily determined to replace with scan FFs or registers in the full scan process, in a sort order obtained in the sorting process, whether or not the integrated circuit has an n-fold line-up structure in assuming the FF or register to replace with a non-scan FF or register, and temporarily identifying the FF or register as a non-scan FF or register when the integrated circuit has an n-fold line-up structure by said assumption, wherein an FF or register temporarily identified as a scan FF or register as a result of executing the non-scan selecting process is defined as a scan FF or register.
In this method, respective FFs or registers are subjected to the scan FF or register identification in a sort order according to the predetermined evaluation function indicating the degree of relation with difficulty in generating test sequences. Accordingly, a circuit for which test sequences can be easily generated is obtained, resulting in improving the fault efficiency as compared with that achieved by the conventional technique.
The sorting process preferably comprises the steps of recognizing a balanced reconvergence structure included in the integrated circuit; and sorting the FFs or registers with using a function indicating a degree of relation with the recognized balanced reconvergence structure as the predetermined evaluation function. Alternatively, the sorting process preferably comprises the step of sorting the FFs or registers with using a number of inputs/outputs of each FF or register in an FF relation graph or a register relation graph representing the integrated circuit as the predetermined evaluation function. Alternatively, the sorting process preferably comprises the step of sorting the FFs or registers with using a result of a predetermined calculation using a maximum sequential input distance and a maximum sequential output distance as the predetermined evaluation function.
Alternatively, the method of design for testability of this invention for modifying design of an integrated circuit designed at gate level or register transfer level, in order to attain testability after manufacture, comprises a step of identifying a scan FF or register in the integrated circuit so that the integrated circuit does not have a balanced reconvergence structure satisfying a predetermined condition.
The predetermined condition is preferably having a depth of a predetermined number or more, including a predetermined number or more paths, or including a predetermined number or more FFs.
Alternatively, the method of design for testability of this invention for modifying design of an integrated circuit designed at gate level or register transfer level, in order to attain testability after manufacture, comprises a step of identifying a scan flip-flop (FF) or register in the integrated circuit so that the integrated circuit has an n-fold line-up structure, wherein the identification step comprises the steps of sorting FFs or registers in the integrated circuit in accordance with a predetermined evaluation function indicating a degree of relation with difficulty in generating test sequences; and determining for each of the FFs or registers in the integrated circuit whether or not to replace with a scan FF or register in a sort order obtained in the sorting process.
Alternatively, the method of design for testability of this invention for modifying design of an integrated circuit designed at gate level or register transfer level, in order to attain testability after manufacture, comprises a step of identifying a scan flip-flop (FF) or register in the integrated circuit so that the integrated circuit has an n-fold line-up structure, wherein the identification step comprises the steps of searching a single-output FF or a single-output register in the integrated circuit; and identifying the searched single-output FF or single-output register as a non-scan FF or register.
Alternatively, the method of design fo

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