Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-04-24
2001-06-26
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06253343
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to design for testability and test sequence generation for integrated circuits (LSIs).
Scan design is a conventionally used design as a typical design for testability technology. In a scan design method, flip-flops (FFs) in a logic-designed integrated circuit are replaced by scan FFs and hence can be controlled (scan-in) and observed (scan-out) directly from outside and the problem of sequential circuits is simplified into that of combinational circuits, for test sequence generation facilitation. One such technology is described in Digital Systems Testing and Testable Design, Chapter 9, Design For Testability, published in 1990 by Computer Science Press.
Scan design may be classified into two types, namely a full scan design method and a partial scan design method. In the former design method, all FFs in a circuit are replaced by scan FFs. On the other hand, in the latter design method, only some FFs in a circuit are replaced by scan FFs. A method of identifying (selecting) scan FFs in the partial scan design is fully discussed in a paper, entitled An Exact Algorithm for Selecting Partial Scan Flip-Flops, DAC (Design Automation Conference), pp.81-86, 1994 as well as in its references.
Additionally, as to test sequence generation for sequential circuits, test sequence compaction is fully described in a paper entitled Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Technique, FTCS (Fault Tolerant Computing Symposium), pp. 53-61, 1996 as well as in its references.
The above-noted prior art techniques however have their respective problems. A conventional partial scan design method produces the problem that in identification of FFs to replace with scan FFs it is not always possible to guarantee sufficiently high fault efficiency, i.e., 95% or more. Additionally a conventional test sequence compaction method for sequential circuits also produces the problem that it is poor in compaction rate.
SUMMARY OF THE INVENTION
An object of the invention is to provide an improved method of design for testability to guarantee a high fault efficiency in identifying FFs to replace with scan FFs. Another object of the invention is to provide an improved method of test sequence generation able to achieve a higher compaction rate in comparison with the prior art techniques.
This invention provides a method of design for testability for modifying design of an integrated circuit designed at gate level, in order to attain testability after manufacture, comprising the step of selecting flip-flops to replace with scan flip-flops among flip-flops in said integrated circuit in order that said integrated circuit has an n-fold line-up structure.
It is preferred that the method of design for testability comprises:
a full scan step of temporarily selecting about all flip-flops in said integrated circuit as flip-flops to replace with scan flip-flops; and
a non-scan flip-flop selection step of examining, for each of the flip-flops temporarily selected as flip-flops to replace with scan flip-flops by said full scan step, that is, temporary scan flip-flop, whether said integrated circuit has an n-fold line-up structure or not in assuming each said temporary scan flip-flop as flip-flops to replace with non-scan flip-flops, and temporarily selecting, when said integrated circuit has an n-fold line-up structure by said assumption, each said temporary scan flip-flop as a flip-flop to replace with a non-scan flip-flop,
wherein the flip-flops temporarily selected as flip-flops to replace with scan flip-flops by said full scan step and said non-scan flip-flop selection step are finally selected as flip-flops to replace with scan flip-flops.
This invention provides another method of design for testability for modifying design of an integrated circuit designed at gate level in order to attain testability after manufacture, comprising:
a first step of selecting, with recognizing load/hold flip-flop as not having a self-loop structure, flip-flops to replace with scan flip-flops among flip-flops in said integrated circuit in order that said integrated circuit has an n-fold line-up structure; and
a second step of selecting flip-flops to replace with scan flip-flops so as to attain testability on load/hold flip-flops, in said integrated circuit with the flip-flops to replace with scan flip-flops selected at said first step.
It is preferred that in the method of design for testability said second step includes:
performing timeframe expansion, based on the state justification of load/hold flip-flops, about said integrated circuit with the flip-flops to replace with scan flip-flops selected at said first step, and selecting flip-flops to replace with scan flip-flops from said timeframe expansion.
This invention provides a method of test sequence generation for an integrated circuit, comprising:
a buffer length set step of setting a buffer length for a buffer for storing a test sequence; and
test sequence compaction step of generating a test sequence for said integrated circuit, in performing sequentially compaction storage of test sequences for respective faults in buffers having said buffer length set in said buffer length set step.
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“Design for Testability”, Publication by Computer Science Press, Chapter 9, pp. 343-395, 1990.
S.T. Chakradhar, et al., An Exact Algorithm for Selecting Partial Scan Flip-Flops, Proceedings of 31stACM/IEEE Design Automation Conference, pp. 81-86, 1994.
I. Pomeranz, et al., “Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques”, Proceedings of FTCS-26, pp. 53-61, 1996.
R. K. Roy, et al., Compaction of ATPG-Generated Test Sequences for Sequential Circuits, Proceedinds of 1998 IEEE, pp. 382-385, 1988.
Kunzmann et al., “An Analytical Approach to the Partial Scan Problem”; Journal of Electronic Testing, vol. 1, No. 2, May 1990, pp. 163-174.
Niermann et al., “Test Compaction for Sequential Circuits”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 11, No. 2, Feb. 1992, pp. 260-267.
Hosokawa et al., “A Partial Scan Design Method Based on n-Fold Line-up Structures”, Proceedings Sixth Asian Test Symposium (ATS'97), NOV97, pp. 306-311.
Transactions of Institute of Electronics D-I vol. J80-D-I No. 2, Feb. 1997.
Bhawmik, et al., Pascant a Partial Scan and test Generation System, IEEE, 1991.*
Cheng, Partial Scan Designs Without Using a Separate Scan Clock, IEEE, 1995.*
Oyama, et al., Scan Design Oriented Test Technique for VLSI,s Using ATE, IEEE, 1996.*
O'Connor, A Methodology for Programmable Logic Migration to ASIC's Including Automatic Scan Chain Insertion and ATPG, IEEE, 1991.
Hosokawa Toshinori
Ohta Mitsuyasu
De'cady Albert
Lamarre Guy
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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