Method of and system for testing an integrated circuit

Details Method of and system for testing an integrated circuit Method of and system for testing an integrated circuit

2005-09-08

2009-11-17

Ellis, Kevin L (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S047300, C714S048000, C714S055000, C713S500000

Reexamination Certificate

active

07620862

ABSTRACT:
The methods and circuits of the present invention relate to testing integrated circuits. According to one aspect of the invention, a method of testing an integrated circuit is disclosed. The method comprises the steps of coupling test equipment to the integrated circuit; coupling a test equipment clock signal from the test equipment to the integrated circuit, wherein the test equipment clock signal has a first frequency; generating an internal burst clock signal within the integrated circuit based upon the test equipment clock signal, wherein the internal test clock signal has a burst frequency; and testing the integrated circuit using the internal burst clock signal. Other methods and circuits for testing programmable logic devices are also described.

REFERENCES:
patent: 4791356 (1988-12-01), Warren et al.
patent: 5177440 (1993-01-01), Walker et al.
patent: 5381087 (1995-01-01), Hirano
patent: 5948105 (1999-09-01), Skurnik et al.
patent: 6047344 (2000-04-01), Kawasumi et al.
patent: 6145087 (2000-11-01), Ishihara
patent: 6249893 (2001-06-01), Rajsuman et al.
patent: 6430720 (2002-08-01), Frey et al.
patent: 6756827 (2004-06-01), Konuk et al.
patent: 6918074 (2005-07-01), Kim et al.
patent: 7103815 (2006-09-01), Ong et al.
patent: 7197725 (2007-03-01), Takeoka et al.
patent: 7403058 (2008-07-01), Yeh et al.
patent: 2004/0215442 (2004-10-01), Musselman
patent: 2005/0060621 (2005-03-01), Lee et al.
patent: 2005/0218957 (2005-10-01), Konuk et al.
patent: 2006/0080585 (2006-04-01), Kiryu

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