Method of dynamic on-chip digital integrated circuit testing

Details Method of dynamic on-chip digital integrated circuit testing Method of dynamic on-chip digital integrated circuit testing

1997-12-31

2001-04-24

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06223314

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention deals with testing of path delay and stuck-at faults in sensitized paths of digital circuits and digital integrated circuits.
DESCRIPTION OF THE RELATED ART
Testing of digital systems has primarily been to detect steady state malfunctions in logic. This is done using a standard fault model, the “stuck-at 0 or 1” fault, which successfully describes most of the steady-state malfunctions in logic circuits. However, as the structure of logic circuits has become more complex, system timing failures are occurring more frequently. Because the system must operate at higher speeds with greater circuit complexity, the resolution of timing failures is critical to reliable and economical performance.
Timing-related failures may be caused by isolated gate delays or by process-related timing problems that accumulate along logic paths and prevent the circuit from functioning at-speed. The delay faults are becoming critical in deep submicron (DSM) technologies where the interconnect delays exceed the gate delays. Interconnect delay varies as a function of place and route efficiency and process variations and is not predictable at gate level chip simulation. The adoption of DSM technology mandates the use of additional test methods to detect timing-related failures.
In an attempt to identify timing related defects, functional vectors are sometimes applied at-speed on the tester to identify timing-related defects. Although it may improve test quality, this practice suffers from two potential problems. The first problem is the availability of test equipment capable of operating at-speed on modern high speed digital circuits. This kind of test equipment will be very expensive, if not impossible, to construct. Also, input and output pads limit the speed of external functional test vectors. The second problem is that functional vectors applied at-speed may omit critical paths from being tested if the pattern set is not complete and exhaustive.
Timing-related malfunctions are characterized by the concept of delay faults related to circuit critical paths. Conventional techniques for delay test require two distinct primary input vectors that provoke a transition signal at the fault site and propagate the faulty delay effect to a primary output. In the literature, timing related defects have been broadly modeled as gate delay faults or as path delay faults. The gate delay fault model assumes that the incorrect timing behavior of the circuit is due to excess delays in one or more components in the path. Test vector generators based on the gate delay fault model deal with one fault at a time and try to find a test which sensitizes some path through the fault location such that the transition at the output is affected by the target fault. The path delay fault model considers whether the propagation delay through one or more paths exceeds the timing constraint. Therefore, this model makes no assumption about the individual component delays. To be reliable, at least all critical paths in the system should be tested.
In a combinational circuit the path that has the longest propagation time from a primary input to a primary output, called the critical path, determines the operating speed of the circuit. Other paths may have much shorter propagation times and therefore a parametric variation in their delay value may not affect the circuit operating speed unless the changes make their propagation time longer than the critical path delay. However, even a very small increase in the critical path delay will slow down the operating speed of the circuit.
Also in a sequential circuit, the system is free of timing failures if every combinatorial path between two memory elements propagates its signal in less time than the interval of the operating system clock. In other words, the input signal of every memory element in the system should have a stable signal before the arrival of the active clock edge. A simplified example of a sequential circuit is shown in FIG.
1
. To make sure that the system is fault-free, the clock period T
CK
should be greater than the sum of the propagation delay of the individual components FFi (t(PD)
FFi
), the propagation delay of the combination circuit (t(PD)
CC
), and the set-up time of the initial component FFo (t(SU)
FF0
).
T
CK
≧t(PD)
FFi
+t(PD)
CC
+t(SU)
FF0
  (1)
The above relationship can be rewritten as follows
T
CK
−t(PD)
FFi
−t(SU)
FF0
≧t(PD)
CC
  (2)
Therefore a given delay increase in a path may result in a malfunction in the circuit, but the same delay increase in another path may not affect the circuit functionality and performance. If the only test target is the propagation delay regardless of the circuit functionality, a delay fault on a path that does not affect the circuit performance will result in the rejection of a circuit that is functionally acceptable. This may lead to a large number of false rejections of acceptable circuits resulting a significant yield loss.
BRIEF SUMMARY OF THE INVENTION
A method and associated circuitry test propagation delay through a path in digital circuits and integrated circuits. The method first sensitizes the target path in the circuit. Then depending on the path a feedback is established between the output and the input of the path to construct an inverting loop. If the path is inverting, the feedback will be noninverting and if the path is noninverting, the feedback will be inverting.
The inverting loop or ring carries oscillation signals. In one implementation, the feedback element is connected using a multiplexer coupled to the circuit under test. As the oscillation frequency is determined by the propagation delay through the path, it can be used to measure the path propagation delay. Any kind of faults that can stop the oscillations, such as stuck at faults in the loop, can be detected by observing the oscillation frequency.
Additional objects and advantages of the present invention will be apparent from the detailed description of the preferred embodiment thereof, which proceeds with reference to the accompanying drawings.


REFERENCES:
patent: 5553082 (1996-09-01), Conner et al.
patent: 5617426 (1997-04-01), Koenemann et al.
patent: 5774476 (1998-06-01), Pressly et al.
patent: 5811655 (1998-09-01), Hashimoto et al.
patent: 5867033 (1999-02-01), Sporck et al.

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