Address and TMS gating circuitry for TAP control circuit

Address conversion device for nonvolatile memory

Address counter for addressing synchronous high-frequency...

Address counter test mode for memory device

Address decoding system and method for failure toleration in...

Address error detection by merging a polynomial-based CRC...

Address generation apparatus for turbo interleaver and...

Address generation for contention-free memory mappings of...

Address generator

Address generator for block interleaving

Address generator for generating addresses for testing a...

Address generator, interleave unit, deinterleaver unit, and...

Address information detecting apparatus and address...

Address parity error processing method, and apparatus and...

Address sequencer within BIST (Built-in-Self-Test) system

Address trap comparator capable of carrying out high speed...

Addressable tap domain selection circuit with TDI/TDO...

Addressing scheme for convolutional interleaver/de-interleaver

Addressing strategy for Viterbi metric computation

Adjustable voltage boundary scan adapter for emulation and test